IP Library Granted Patent US 10,643,959
Granted Patent B2
US 10,643,959 · App. 15/453,889 · Granted May 5, 2020

Method of making a stacked inductor-electronic package

Inventors: Zaki Moussaoui (Palm Bay, FL); Nikhil Vishwanath Kelkar (Saratoga, CA)
Assignee: Intersil Americas LLC
H01L23/645H01L23/3107H01L23/3675H01L23/481H01L23/495H01L23/49531H01L23/49555H01L23/49575H01L24/96H01L25/165H01L25/50H05K3/3447H05K3/3484H05K3/3494H01L2924/0002H01L2924/13091H01L2924/14H01L2924/1433H01L2924/19041H01L2924/19042H01L2924/19043H01L2924/19102H01L2924/19105Y10T29/4902
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Quick Facts
Patent No.
US 10,643,959
App. No.
15/453,889
Granted
May 5, 2020
Kind
B2
Abstract

An embodiment of a circuit includes a circuit module and an inductor disposed over and electrically coupled to the module. Disposing the inductor over the module may reduce the area occupied by the circuit as compared to a circuit where the inductor is disposed adjacent to the module, or to a circuit where the inductor is disposed in the module adjacent to other components of the module. Furthermore, disposing the inductor outside of the module may allow one to install or replace the inductor.

Claims (15)

1. A method, comprising:

fabricating a batch of a plurality of inductors connected to each other;

fabricating a batch of modules;

attaching the batch of inductors to the batch of modules; and

separating the plurality of inductors from each other to create a plurality of assemblies, each assembly including a respective one of the plurality of inductors stacked on top of a module.

2. The method of claim 1 wherein attaching the inductors to the modules includes inserting straight leads of the inductors into Vertical Interconnect Access (VIA) holes of the modules.

3. The method of claim 2 wherein attaching the inductors to the modules includes filling the VIA holes of the electronic package with solder paste and attaching the inductors to the solder paste at the top of the holes.

4. The method of claim 3 , further comprising:

running the reflow process for filling the VIA holes with solder paste; and

running the reflow process again to attach the inductors to the solder paste at the top of the holes.

5. The method of claim 1 wherein attaching the inductors to the modules includes bending external leads of the modules into reverse J-bend configurations, and attaching the inductors to the leads using solder paste.

6. The method of claim 1 wherein,

the inductors are connected to each other with strips of insulating material; and

the separation of the inductors from each other is performed by using a cutting technique.

7. The method of claim 1 wherein fabricating the batch of inductors is performed at a first facility and fabricating the batch of electronic packages is performed in at a second facility that is different than the first facility.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 8, 2017
From: MOUSSAOUI, ZAKI; KELKAR, NIKHIL VISHWANATH
To: INTERSIL AMERICAS INC.
Reel/Frame 041511/0082 →
CHANGE OF NAME Recorded Mar 8, 2017
From: INTERSIL AMERICAS INC.
To: INTERSIL AMERICAS LLC
Reel/Frame 041924/0802 →
Continuity (3)
Division 12962053 · Dec 7, 2010
Provisional Application 61267117 · Dec 7, 2009
Related Publication 20170179048A1 · Jun 22, 2017