Semiconductor device having buried metal line and fabrication method of the same
A device is disclosed that includes a memory bit cell, a first word line, a pair of metal islands and a pair of connection metal lines. The first word line is disposed in a first metal layer and is electrically coupled to the memory bit cell. The pair of metal islands are disposed in the first metal layer at opposite sides of the word line and are electrically coupled to a power supply. The pair of connection metal lines are disposed in a second metal layer and are configured to electrically couple the metal islands to the memory bit cell respectively.
1. A device, comprising:
a semiconductor substrate;
a fin field effect transistor (FinFet) comprising:
a fin over the semiconductor substrate;
a gate structure over the fin; and
a source/drain structure adjoining the fin and adjacent to the gate structure;
a shallow trench isolation structure surrounding the fin;
a buried metal line under a top surface of the shallow trench isolation structure; and
a metal segment over the source/drain structure, wherein a portion of the metal segment extends into the shallow trench isolation structure to be electrically coupled to the buried metal line.
2. The device of claim 1 , further comprising:
a barrier layer between the buried metal line and the semiconductor substrate.
3. The device of claim 2 , further comprising a glue layer between the barrier layer and the buried metal line.
4. The device of claim 3 , wherein the barrier layer comprises SiOx, SiN or a combination thereof, and the glue layer comprises TiN, TaN or a combination thereof.
5. The device of claim 1 , further comprising an electrical component over the first fin, wherein the metal segment is disposed over the electrical component.
6. The device of claim 1 , further comprising;
an interlayer dielectric portion around the metal segment;
a dielectric layer over the metal segment and the interlayer dielectric portion; and
at least one top metal line on the dielectric layer, wherein a portion of the at least one top metal line extends through the dielectric layer to be electrically coupled to the metal segment.
7. The device of claim 1 , wherein the buried metal line is a power line or a signal line.
8. A device, comprising:
a shallow trench isolation structure comprising trenches filled with dielectric material;
an electrical component on the shallow trench isolation structure;
a buried metal line at least partially within a first trench of the trenches or under the first trench;
a barrier layer formed to isolate the buried metal line from the first trench that is filled with dielectric material; and
a metal segment partially over the electrical component, wherein a portion of the metal segment extends to the first trench to be electrically coupled to the buried metal line.
9. The device of claim 8 , wherein material of the barrier layer comprises SiOx, SiN or a combination thereof.
10. The device of claim 8 , further comprising:
a glue layer formed between the barrier layer and the buried metal line.
11. The device of claim 10 , wherein material of the glue layer comprises TiN, TaN or a combination thereof.
12. The device of claim 8 , further comprising:
at least one top metal line over the metal segment, wherein a portion of the at least one top metal line extends to be electrically coupled to the metal segment.
13. The device of claim 8 , further comprising:
an interlayer dielectric portion around the metal segment;
a dielectric layer over the metal segment and the interlayer dielectric portion; and
at least one top metal line formed on the dielectric layer, wherein a portion of the at least one top metal line extends through the dielectric layer to be electrically coupled to the metal segment.
14. The device of claim 8 , wherein the buried metal line is a power line or a signal line.
15. A device, comprising:
an isolation structure on a semiconductor substrate;
a buried metal line under a top surface of the isolation structure;
a metal segment partially over the isolation structure, wherein a portion of the metal segment extends into the isolation structure to be electrically coupled to the buried metal line;
a dielectric layer over the metal segment; and
at least one top metal line on the dielectric layer, wherein a portion of the at least one top metal line extends through the dielectric layer to be electrically coupled to the metal segment.
16. The device of claim 15 , further comprising:
a barrier layer between the buried metal line and the semiconductor substrate.
17. The device of claim 16 , further comprising:
a glue layer between the barrier layer and the buried metal line.
18. The device of claim 17 , wherein the barrier layer comprises SiOx, SiN or a combination thereof, and the glue layer comprises TiN, TaN or a combination thereof.
19. The device of claim 15 , further comprising:
an electrical component over the isolation structure, wherein the metal segment is disposed over the electrical component.
20. The device of claim 15 , wherein the buried metal line is a power line or a signal line.