Functional prober chip
Systems, devices, and methods for characterizing semiconductor devices and thin film materials. The device consists of multiple probe tips that are integrated on a single substrate. The layout of the probe tips could be designed to match specific patterns on a CMOS chip or sample. The device provides for detailed studies of transport mechanisms in thin film materials and semiconductor devices.
1. A CMOS prober chip, the CMOS prober chip comprising:
a plurality of probe tips, wherein each of the plurality of probe tips are spring-loaded and each of the plurality of probe tips comprises an apex at an end of each respective probe tip, the apex comprising a conductive material, the conductive material arranged to reversibly deform when in contact with a sample;
a plurality of interlayer metals;
a plurality of interlayer dielectrics; and
a plurality of bonding pads;
wherein the plurality of interlayer metals are in conductive communication with the conductive material of the plurality of probe tips, and are further in conductive communication with the plurality of bonding pads and wherein the conductive material is deposited over the apex of each respective probe tip; wherein the conductive material and the plurality of probe tips are formed as portions of the same CMOS prober chip on a single substrate.
2. The CMOS prober chip of claim 1 , wherein the conductive material comprises a thin film material selected from a group consisting of graphene and molybdenum disulphide.
3. The CMOS prober chip of claim 1 , wherein the conductive material comprises a metal or metal-alloy.
4. The CMOS prober chip of claim 1 , wherein each of the plurality of probe tips comprises a metal contact plug.
5. The CMOS prober chip of claim 4 , wherein the metal contact plug comprises tungsten, platinum, gold, cobalt, nickel, an alloy, and/or silicide.
6. The CMOS prober chip of claim 1 , wherein at least one of the plurality of probe tips is freely suspended along at least a portion of its length.
7. A method for manufacturing the CMOS prober chip of claim 1 , the method comprising the step of selectively depositing the conductive material at an apex of each of the plurality of probe tips and wherein the step of selectively depositing a conductive material comprises electroplating, evaporation, sputtering, plasma enhanced chemical vapor deposition, and/or atomic layer deposition.
8. A prober chip, the prober chip comprising:
a plurality of spring-loaded probe tips, the plurality of probe tips each including an apex and each apex comprises a deposited conductive material, wherein the plurality of spring-loaded probe tips are configured to reversibly conform and the conductive material is arranged to reversibly deform when in contact with a sample;
a plurality of interlayer metals;
a plurality of interlayer dielectrics;
a plurality of through-substrate-vias;
a plurality of bonding pads; and
a substrate;
wherein the plurality of interlayer metals are in conductive communication with the plurality of probe tips, and are further in conductive communication with the plurality of bonding pads and wherein the deposited conductive material is deposited over the apex of each respective probe tip; wherein the conductive material and the plurality of probe tips are formed as portions of the same CMOS prober chip on a single substrate.
9. The prober chip of claim 8 , wherein at least some of the plurality of probe tips are freely suspended along at least a portion of their length.
10. The prober chip of claim 8 , wherein each of the plurality of through-substrate-vias is filled with a conductive material configured to conductively connect the bonding pads to the plurality of interlayer metals.
11. The prober chip of claim 8 , wherein the substrate comprises silicon, silicon carbide, germanium, glass, pyrex, fused silica and/or quartz.