CMOS input buffer with low supply current and voltage down shifting
A method for implementing a CMOS input buffer that consumes very low current even when input levels are less than full swing. An additional optional stage enables conversion to very low voltage swing. The circuit can be manufactured with a standard CMOS processing technology and with high immunity to variation of process parameters. The circuit provides some hysteresis response, enhancing the input voltage margin.
1. An input buffer circuit comprising:
a first stage, comprising:
a first CMOS inverter circuit comprising pull-down n-channel field effect transistors, wherein a gate of a first transistor of the three n-channel field effect transistor is connected to an input of the circuit, and the source of the first transistor is connected to one or several serially diode-connected n-channel field effect transistors, said serially diode-connected n-channel field effect transistors have gates connected to the drain, wherein the source of the most bottom transistor of said serially diode-connected n-channel field effect transistors is connected to a negative supply voltage of the circuit, and another n-channel field effect transistor has a source connected to the negative supply voltage and drain connected to the drain of the serially diode-connected n-channel field effect transistors, wherein the gate is connected to the output of an inverter that inverts the output of the first stage of the input buffer;
said CMOS inverter circuit further comprises pull-up p-channel field effect transistors, wherein a gate of the p-channel field effect transistor is connected to the input of the circuit, and the source is connected to one or several serially diode-connected p-channel field effect transistors have gates connected to the drain, wherein the source of the most upper transistor is connected to the positive supply voltage, and another p-channel field effect transistors with source connected to the positive supply voltage and drain connected to the drain of the serially diode-connected p-channel field effect transistors, wherein the gate is connected to the output of an inverter that inverts the output of the first stage of the input buffer.
2. The input buffer of claim 1 wherein the n-channel and p-channel field effect transistors, whose gate is connected to the input pad of the integrated circuit, are forming any CMOS logic function.
3. The input buffer of claim 1 wherein only the pull-down n-channel field effect transistors are connected as described in claim 1 .
4. The input buffer of claim 1 wherein only the pull-up p-channel field effect transistors are connected as described in claim 1 .
5. The input buffer of claim 1 , wherein said buffer can be used as an input stage between different power domains within the same or different integrated circuits.
6. The input buffer of claim 1 , further comprising an additional inverting stage of the input buffer comprising:
a pull-down n-channel field effect transistor whose gate is connected to the previous stage, the source is connected to the negative supply voltage of the power domain that is driven by the circuit and a drain connected to the output of the circuit;
an additional pull-up n-channel field effect transistor whose gate is connected to an output of the previous stage and has a logic state that is opposite than the inverted output of the previous stage, the drain is connected to the positive supply voltage of the power domain driven by the circuit, said supply voltage is equal or lower than the supply voltage of the power domain of the previous stage, and a source connected to the output of this circuit.
7. The input buffer of claim 6 wherein one of the p-channel field effect transistors is also connected to the pull-up n-channel field effect transistor, whose gate is connected to the output of the previous stage, the source is connected to the positive supply voltage of the power domain driven by the circuit and the drain is connected to the output of the circuit.