Memory control circuitry, memory system and processor system
View Patent ↗A memory control circuitry has a write destination selector to select either a volatile memory or a non-volatile memory in a first storage as a write destination, for an address area in the first storage written by a processor, a write controller to write data in the write destination selected by the write destination selector, and an access information register to register information selecting the volatile memory or the non-volatile memory as the write destination, and number-of-times information indicating how many times a page of successive addresses for the address area is switched, as both information being associated with each other. When there is a write request from the processor, the write destination selector selects the write destination based on the information registered in the access information register.
1. A memory control circuitry comprising:
a write destination selector to select either a volatile memory or a non-volatile memory in a first storage as a write destination, for an address area in the first storage written by a processor;
a write controller to write data in the write destination selected by the write destination selector; and
an access information register to register information selecting the volatile memory or the non-volatile memory as the write destination, and number-of-times information indicating how many times a page of successive addresses for the address area is switched, as both information being associated with each other,
wherein, when there is a write request from the processor, the write destination selector selects the write destination based on the information registered in the access information register, and updates the information registered in the access information register, and
wherein the access information register comprises:
a switching times acquirer to acquire page switching times in order from a largest number of page switching times for data written to the volatile memory and to acquire a smallest number of page switching times for data written to the nonvolatile memory when there is the write request from the processor,
a switching times determiner to determine whether the acquired page switching times for the volatile memory is larger than the acquired smallest number of page switching times for the nonvolatile memory, and
a replacement unit to replace data in the volatile memory with data in the non-volatile memory when determined to be larger.
2. The memory control circuitry of claim 1 , wherein the write destination selector updates the information in the access information register when the processor issues a write request to a write destination not registered in the access information register or when the number-of-times information in the access information register is updated.
3. The memory control circuitry of claim 1 , wherein the address area is a partial storage area in the first storage, the partial storage area being accessed by a thread to be executed by the processor.
4. The memory control circuitry of claim 3 , wherein a plurality of threads are provided; and
the access information register registers physical address information identifying the address area, identification information identifying the thread, number-of-times information indicating how many times the page to be accessed by the thread is switched, and information selecting the volatile memory or the non-volatile memory as the write destination, as these information being associated with one another for the thread.
5. The memory control circuitry of claim 1 , wherein the address area is a partial storage area in the first storage, the partial storage area being accessed with address conversion information converting a virtual address group for accessing the page into a physical address group.
6. The memory control circuitry of claim 5 , wherein the access information register registers physical address information identifying the address area, identification information identifying the thread, number-of-times information indicating how many times the page to be accessed with the address conversion information is switched, and information selecting the volatile memory or the non-volatile memory as the write destination, as these information being associated with one another for the address conversion information.
7. The memory control circuitry of claim 1 , wherein the write destination selector selects either the volatile memory or the non-volatile memory as the write destination when a write request address issued by the processor is not present in a second storage having a higher access priority than the first storage.
8. The memory control circuitry of claim 1 further comprising:
a first free-space determiner to determine whether the non-volatile memory has a free space; and
a second free-space determiner to determine whether the volatile memory has a free space,
wherein, when it is determined that the non-volatile memory and the volatile memory both have the free space, the write destination selector selects one memory having a larger free space of the non-volatile memory and the volatile memory as the write destination, when it is determined that the non-volatile memory has the free space and the volatile memory has no free space, the write destination selector selects the non-volatile memory as the write destination, and when it is determined that the volatile memory has the free space and the non-volatile memory has no free space, the write destination selector selects the volatile memory as the write destination.
9. The memory control circuitry of claim 1 ,
wherein the access information register sorts data stored in the volatile memory per address area based on the number-of-times information, and
wherein the write controller moves data of an address area of a page of a larger number of switching times, to the non-volatile memory based on data per the sorted address area.
10. The memory control circuitry of claim 1 further comprising an average value detector to count switching times of the page per address area for a predetermined period of time and obtains an average value of the switching times of the page,
wherein the write destination selector selects either the volatile memory or the non-volatile memory as the write destination by comparing the switching times of the page associated with write request data from the processor with the average value.
11. The memory control circuitry of claim 10 , wherein, when the switching times of the page associated with write request data from the processor is larger than the average value, and if the non-volatile memory has a free space, the write destination selector selects the non-volatile memory as the write destination, and if the non-volatile memory has no free space, the write destination selector moves data in an address area with a smaller number of switching times of the page to the volatile memory and selects the volatile memory as the write destination, and
when the switching times of the page associated with write request data from the processor is equal to or smaller than the average value, and if the volatile memory has a free space, the write destination selector selects the volatile memory as the write destination, and if the volatile memory has no free space, the write destination selector moves data in an address area with a larger number of switching times of the page to the non-volatile memory and selects the volatile memory as the write destination.
12. A memory system comprising:
a first storage comprising a non-volatile memory and a volatile memory;
a write destination selector to select either the volatile memory or the non-volatile memory in the first storage, as a write destination, for an address area in the first storage written by a processor;
a write controller to write data in the write destination selected by the write destination selector; and
an access information register to register information selecting the volatile memory or the non-volatile memory as the write destination, and number-of-times information indicating how many times a page of successive addresses for the address area is switched, as both information being associated with each other,
wherein, when there is a write request from the processor, the write destination selector selects the write destination based on the information registered in the access information register, and updates the information registered in the access information register, and
wherein the access information register comprises:
a switching times acquirer to acquire page switching times in order from a largest number of page switching times for data written to the volatile memory and to acquire a smallest number of page switching times for data written to the nonvolatile memory when there is the write request from the processor,
a switching times determiner to determine whether the acquired page switching times for the volatile memory is larger than the acquired smallest number of page switching times for the nonvolatile memory, and
a replacement unit to replace data in the volatile memory with data in the non-volatile memory when determined to be larger.
13. The memory system of claim 12 , wherein the write destination selector updates the information in the access information register when the processor issues a write request to a write destination not registered in the access information register or when the number-of-times information in the access information register is updated.
14. The memory system of claim 12 , wherein the address area is a partial storage area in the first storage, the partial storage area being accessed by a thread to be executed by the processor.
15. The memory system of claim 14 , wherein a plurality of threads are provided; and
the access information register registers physical address information identifying the address area, identification information identifying the thread, number-of-times information indicating how many times the page to be accessed by the thread is switched, and information selecting the volatile memory or the non-volatile memory as the write destination, as these information being associated with one another for the thread.
16. The memory system of claim 12 , wherein the address area is a partial storage area in the first storage, the partial storage area being accessed with address conversion information converting a virtual address group for accessing the page into a physical address group.
17. A processor system comprising:
a processor;
a first storage to be accessed by the processor, the first storage comprising a non-volatile memory and a volatile memory;
a write destination selector to select either the volatile memory or the non-volatile memory in the first storage, as a write destination, for an address area in the first storage written by a processor;
a write controller to write data in the write destination selected by the write destination selector; and
an access information register to register information selecting the volatile memory or the non-volatile memory as the write destination, and number-of-times information indicating how many times a page of successive addresses for the address area is switched, as both information being associated with each other,
wherein, when there is a write request from the processor, the write destination selector selects the write destination based on the information registered in the access information register, and updates the information registered in the access information register, and
wherein the access information register comprises;
a switching times acquirer to acquire page switching times in order from a largest number of page switching times for data written to the volatile memory and to acquire a smallest number of page switching times for data written to the nonvolatile memory when there is the write request from the processor,
a switching times determiner to determine whether the acquired page switching times for the volatile memory is larger than the acquired smallest number of page switching times for the nonvolatile memory, and
a replacement unit to replace data in the volatile memory with data in the non-volatile memory when determined to be larger.