Circuit device, physical quantity detection device, oscillator, electronic apparatus, vehicle, and method of detecting failure of master clock signal

1. A circuit device comprising:

a control circuit that operates on the basis of a master clock signal;

and an interface circuit that includes a register unit and transmits data on the basis of an external clock signal which is input from an external device,

wherein the register unit takes up error information of the master clock signal on the basis of the external clock signal and stores the taken-up error information, and

wherein the interface circuit transmits the data, including the error information stored in the register unit.

2. The circuit device according to claim 1 , further comprising:

a master clock signal failure detection circuit that detects a failure of the master clock signal and outputs the error information,

indicating that the master clock signal is set to be in a failure state, to the register unit in a case where the failure is detected.

3. The circuit device according to claim 2 ,

wherein the register unit takes up the error information from the master clock signal failure detection circuit on the basis of the external clock signal.

4. The circuit device according to claim 2 ,

wherein the master clock signal failure detection circuit detects a failure of the master clock signal on the basis of an error detection clock signal which is a clock signal different from the master clock signal, and outputs the error information to the register unit.

5. The circuit device according to claim 4 , further comprising:

a driving circuit that oscillates a vibrator,

wherein the error detection clock signal is a clock signal which is generated by oscillating the vibrator.

6. The circuit device according to claim 2 ,

wherein the master clock signal failure detection circuit includes a first flip flop circuit that latches an input clock signal based on the master clock signal,

on the basis of an error detection clock signal which is a clock signal different from the master clock signal,

a second flip flop circuit that latches a first output signal from the first flip flop circuit on the basis of the error detection clock signal,

an exclusive OR circuit that obtains an exclusive OR of the first output signal and a second output signal from the second flip flop circuit,

and a counter that counts a period of time for which an output signal of the exclusive OR circuit is set to be a first logic level,

on the basis of the error detection clock signal,

and outputs the error information indicating that the master clock signal is set to be in a failure state,

in a case where a counted value is set to be a predetermined value.

7. The circuit device according to claim 1 , further comprising:

a defect diagnosis circuit that operates by the master clock signal,

wherein the register unit includes a failure diagnosis resister that takes up error information from the defect diagnosis circuit.

8. The circuit device according to claim 1 ,

wherein the interface circuit is an interface circuit of a serial peripheral interface (SPI) system or an inter-integrated circuit (I2 C) system.

9. The circuit device according to claim 1 ,

further comprising:

a master clock signal generation circuit that generates the master clock signal.

10. A circuit device comprising:

a master clock signal failure detection circuit that detects a failure of a master clock signal;

and a register circuit that takes up error information of the master clock signal on the basis of an external clock signal which is input from an external device comprising a central processing unit (CPU).

11. The circuit device according to claim 10 ,

further comprising:

an interface circuit that transmits data including the error information stored in the register circuit on the basis of the external clock signal.

12. A circuit device comprising:

a failure detection circuit that detects a failure of a first clock signal on the basis of a second clock signal different from the first clock signal;

and a register circuit that takes up error information of the first clock signal on the basis of a third clock signal which is an external clock signal input from an external device comprising a central processing unit (CPU),

wherein each of the first clock signal, the second clock signal and third clock signal are different clock signals from each other.

13. A method of detecting a failure of a master clock signal,

the method comprising:

detecting a failure of the master clock signal by a clock signal other than the master clock signal;

taking up error information of the master clock signal in a register circuit on the basis of an external clock signal which is input from an external device comprising a central processing unit (CPU);

and transmitting data including the error information stored in the register circuit on the basis of the external clock signal,

wherein each of the clock signal, the external clock signal and the master clock signal are different clock signals from each other.

14. A physical quantity detection device comprising:

the circuit device according to claim 1 ;

and a physical quantity transducer.

15. The physical quantity detection device according to claim 14 ,

wherein the physical quantity transducer is at least one of an acceleration detection element and an angular velocity detection element.

16. An oscillator comprising: the circuit device according to claim 1 ; and a vibrator.

17. An electronic apparatus comprising the circuit device according to claim 1 .

18. A vehicle comprising the circuit device according to claim 1 .