IP Library Granted Patent US 10,083,979
Granted Patent B2
US 10,083,979 · App. 15/462,619 · Granted Sep 25, 2018

Semiconductor device, manufacturing method and controlling method of semiconductor device

Inventor: Kouji Matsuo (Aichi, JP)
Assignee: Toshiba Memory Corporation
H01L27/11575G11C16/0466G11C16/10G11C16/14G11C16/26H01L27/11565H01L27/11568H01L27/11582
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Quick Facts
Patent No.
US 10,083,979
App. No.
15/462,619
Granted
Sep 25, 2018
Kind
B2
Abstract

A semiconductor device includes a substrate, a semiconductor layer, first electrodes, data storage regions, first conductive regions, contacts and second conductive regions. The first electrodes are formed in the semiconductor layer arrayed in a first direction and a second direction and penetrating the insulator films and the semiconductor films in a third direction. The data storage regions are provided between each of the semiconductor films and each of the first electrodes. The first conductive regions are provided at one end of each of the semiconductor films in the first direction. The contacts are connected to one end of one of the first conductive regions in the second direction, and connection parts between each of the contacts and the first conductive regions are formed stepwise along the second direction. The second conductive regions are provided at the other end of the semiconductor layer in the first direction.

Claims (25)

1. A semiconductor device, comprising:

a substrate;

a semiconductor layer on the substrate, the semiconductor layer being formed by alternately laminating a plurality of insulator films and a plurality of semiconductor films;

a plurality of first electrodes formed in the semiconductor layer by being arrayed in a first direction and a second direction and by penetrating the plurality of the insulator films and the plurality of the semiconductor films in a third direction, the first direction being horizontal to a surface of the semiconductor layer, the second direction intersecting with the first direction and being horizontal to the surface of the semiconductor layer, the third direction intersecting with the first direction and the second direction;

a plurality of data storage region provided between each of the semiconductor films and each of the first electrodes;

a plurality of first conductive regions provided at one end of each of the semiconductor films in the first direction; and

a plurality of contacts connected to one end of one of the first conductive regions in the second direction, in which connection parts between each of the contacts and the one of the first conductive regions are formed stepwise along the second direction.

2. The semiconductor device according to claim 1 , further comprising transistors above the semiconductor layer, the transistors being connected to each of the first electrodes.

3. The semiconductor device according to claim 1 , further comprising:

first conducting wirings connected to the first electrodes along the second direction;

a plurality of second electrodes formed in the semiconductor layer by being plurally provided in the first direction at each of both ends of the first electrodes along the first direction and by penetrating the plurality of the insulator films and the plurality of the semiconductor films in the third direction;

transistors connected to each of the second electrodes;

a plurality of second conducting wirings connected to the second electrodes through the plurality of the transistors along the second direction; and

a plurality of third conducting wirings connected to gates of the plurality of the transistors along the first direction.

4. The semiconductor device according to claim 1 , further comprising:

a plurality of first conducting wirings connected to the plurality of the first electrodes along the second direction;

a plurality of second electrodes formed in the semiconductor layer by being plurally provided in the first direction at each of both ends of the first electrodes along the first direction and by penetrating the plurality of the insulator films and the plurality of the semiconductor films in the third direction; and

a plurality of second conducting wirings connected to the plurality of the second electrodes along the first direction.

5. The semiconductor device according to claim 1 , further comprising a plurality of conducting wirings connected to every predetermined number of the plurality of the first electrodes among the plurality of the first electrodes along the second direction.

6. The semiconductor device according to claim 1 , further comprising a plurality of second conductive regions provided at the other end of semiconductor layer in the first direction.

7. The semiconductor device according to claim 6 , further comprising tabular third electrodes along the second direction, the third electrodes being formed in the semiconductor layer by penetrating the plurality of the insulator films and the plurality of the semiconductor films in the third direction and being electrically connected to each of the second conductive regions.

8. The semiconductor device according to claim 6 , further comprising:

first low resistance regions provided in each of the first conductive regions, at an end opposite to the plurality of the first electrodes in the first direction; and

second low resistance regions provided in each of the second conductive regions, at an end opposite to the plurality of the first electrodes in the first direction,

wherein the plurality of the contacts are connected stepwise to each of the first conductive regions through the first low resistance regions provided in each of the first conductive regions.

Assignments (6)
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE POSTAL CODE PREVIOUSLY RECORDED ON REEL 043027 FRAME 0072. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 1, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043747/0273 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 28, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043027/0072 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 12, 2017
From: MATSUO, KOUJI
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 042231/0983 →
Continuity (2)
Provisional Application 62395445 · Sep 16, 2016
Related Publication 20180083026A1 · Mar 22, 2018