Contact formation in semiconductor devices
A technique relates to fabricating a pFET device and nFET device. A contact trench is formed through an inter-level dielectric layer (ILD) and a spacer layer. The ILD is formed over the spacer layer. The contact trench exposes a p-type source/drain region of the pFET and exposes an n-type source/drain region of the NFET. A gate stack is included within the spacer layer. A p-type alloyed layer is formed on top of the p-type source/drain region in the pFET and on top of the n-type source/drain region of the nFET. The p-type alloyed layer on top of the n-type source/drain region of the nFET is converted into a metallic alloyed layer. A metallic liner layer is formed in the contact trench such that the metallic liner layer is on top of the p-type alloyed layer of the pFET and on top of the metallic alloyed layer of the nFET.
1. A method for fabricating a p-type field effect transistor (pFET) device and an n-type field effect transistor (nFET) device, the method comprising:
forming a contact trench through an inter-level dielectric layer and a spacer layer, the inter-level dielectric layer being formed over the spacer layer, the contact trench exposing a p-type source/drain region of the pFET device and exposing an n-type source/drain region of the NFET device, wherein a gate stack is included within the spacer layer;
forming a p-type alloyed layer on top of the p-type source/drain region of the pFET device and on top of the n-type source/drain region of the nFET device;
converting the p-type alloyed layer on top of the n-type source/drain region of the nFET device into a metallic alloyed layer on top of the n-type source/drain region; and
forming a metallic liner layer in the contact trench such that the metallic liner layer is on top of the p-type alloyed layer of the pFET device and on top of the metallic alloyed layer of the nFET device.
2. The method of claim 1 , further comprising forming a conductive contact on top of the metallic liner layer so as to fill the contact trench.
3. The method of claim 1 , wherein the p-type source/drain region is a p-type source/drain material; and
wherein the n-type source/drain region is an n-type source/drain material.
4. The method of claim 3 , wherein the p-type source/drain material is SiGe doped with B.
5. The method of claim 3 , wherein the n-type source/drain material is Si doped with P.
6. The method of claim 1 , wherein the p-type alloyed layer is Ge doped with dopants, the dopants being selected from a group consisting of Ga, B, Al, In, or any combination thereof.
7. The method of claim 1 , wherein converting the p-type alloyed layer on top of the n-type source/drain region of the nFET device into the metallic alloyed layer comprises:
protecting the pFET device by forming a block on top of the pFET device; and
performing ion implantation of ions of material to convert the p-type alloyed layer into an amorphous layer.
8. The method of claim 7 , wherein the ions of material include Sn and P.
9. The method of claim 7 , wherein the amorphous layer is an intermix of Ge, Sn, Ga, and P as a result of the ion implantation.
10. The method of claim 9 , wherein the amorphous layer includes Ge with about 55-60 atomic %, Sn with about 30 atomic %, and P with up to 10 atomic % so as to total 100 atomic %.
11. The method of claim 10 , wherein the atomic % of P is greater that an atomic % of Ga; and
wherein if Ga is 5 atomic %, then P is greater than 5 atomic %.
12. The method of claim 11 , wherein the metallic alloyed layer was doped with dopants selected from a group consisting of p-type dopants, n-type dopants, or a combination of the p-type and the n-type dopants.