Stress relieving through-silicon vias
View Patent ↗Methods and systems for stress relieving through-silicon vias are disclosed and may include forming a semiconductor device comprising a stress relieving stepped through-silicon-via (TSV), said stress relieving stepped TSV being formed by: forming first mask layers on a top surface and a bottom surface of a silicon layer, forming a via hole through the silicon layer at exposed regions defined by the first mask layers, and removing the first mask layers. The formed via hole may be filled with metal, second mask layers may be formed covering top and bottom surfaces of the silicon layer and a portion of top and bottom surfaces of the metal filling the formed via hole, and metal may be removed from the top and bottom surfaces of the metal exposed by the second mask layers to a depth of less than half a thickness of the silicon layer.
1. A method comprising:
forming a via hole through a layer of a semiconductor device such that one or more sidewalls of the via hole extend longitudinally between a first surface and a second surface of the layer;
filling the via hole with metal to form a conductive via that extends along the one or more sidewalls of the via hole; and
forming a stepped via from the conductive via by:
removing, from an upper portion of the conductive via, the metal that extends along a first surface of the one more sidewalls while retaining, in the upper portion of the conductive via, the metal that extends along a second surface of the one or more sidewalls, the second surface being opposite the first surface; and
removing, from a lower portion of the conductive via, the metal that extends along the second surface of the one or more sidewalls while retaining, in the lower portion of the conductive via, the metal that extends along the first surface of the one or more sidewalls.
2. The method of claim 1 , further comprising:
filling, with a conductive material, an upper empty space formed in the via hole by said removing the metal from the upper portion of the conductive via; and
filling, with the conductive material, a lower empty space formed in the via hole by said removing the metal from the lower portion of the conductive via.
3. The method of claim 1 , further comprising:
filling, with a polysilicon, an upper empty space formed in the via hole by said removing the metal from the upper portion of the conductive via; and
filling, with the polysilicon, a lower empty space formed in the via hole by said removing the metal from the lower portion of the conductive via.
4. The method of claim 1 , wherein said filling the via hole with metal comprises filling the via hole with copper.
5. The method of claim 1 , wherein said forming the via hole comprises forming the via hole through the layer of an interposer of the semiconductor device.
6. The method of claim 1 , wherein said forming the via hole comprises forming the via hole through the layer of an integrated circuit die of the semiconductor device.
7. The method of claim 1 , wherein said removing the metal from the upper portion and said removing the metal from the lower portion comprises utilizing an etching process to remove the metal from the upper portion and the lower portion.
8. The method of claim 1 , wherein said removing the metal from the upper portion and said removing the metal from the lower portion comprises utilizing a laser ablating process to remove the metal from the upper portion and the lower portion.
9. The method of claim 1 , further comprising forming a dielectric layer on the one or more sidewalls of the via hole before said filling with the metal.
10. A semiconductor device, comprising:
a layer having an upper surface and a lower surface;
a via hole comprising one or more sidewalls that extend longitudinally between the upper surface and the lower surface of the layer; and
a stepped via comprising metal that extends longitudinally between the upper surface and the lower surface of the layer;
wherein the stepped via comprises an upper portion adjacent the upper surface of the layer, a lower portion adjacent the lower surface of the layer, and a middle portion between the upper and lower portions;
wherein the metal of the upper portion extends along a first surface of the one or more sidewalls, but does not extend along a second surface of the one or more sidewalls, the second surface being opposite the first surface; and
wherein the metal of the lower portion extends along the second surface of the one or more sidewalls, but does not extend along the first surface of the one or more sidewalls.
11. The semiconductor device of claim 10 , wherein:
a conductive material fills a first region of the upper portion, the first region spanning between the metal along the first surface of the one or more sidewalls and the second surface of the one or more sidewalls; and
the conductive material fills a second region of the upper portion, the second region spanning between the metal along the second surface of the one or more sidewalls and the first surface of the one or more sidewalls.
12. The semiconductor device of claim 10 , wherein:
a polysilicon fills a first region of the upper portion, the first region spanning between the metal along the first surface of the one or more sidewalls and the second surface of the one or more sidewalls; and
the polysilicon fills a second region of the lower portion, the second region spanning between the metal along the second surface of the one or more sidewalls and the first surface of the one or more sidewalls.
13. The semiconductor device of claim 10 , wherein the metal is copper.
14. The semiconductor device of claim 10 , further comprising an interposer that includes the layer.
15. The semiconductor device of claim 10 , further comprising an integrated circuit that includes the layer.
16. The semiconductor device of claim 10 , further comprising a dielectric layer on the one or more sidewalls of the via hole.
17. A semiconductor device, comprising:
an integrated circuit die;
a packaging substrate comprising a plurality of conductive traces; and
an interposer disposed between the integrated circuit die and the packaging substrate, the interposer comprising a plurality of stepped vias that extend between an upper surface and a lower surface of the interposer;
wherein the integrated circuit die is electrically coupled to the plurality of conductive traces by way of the plurality of stepped vias; and
wherein each stepped via comprises:
a via hole including one or more sidewalls that extend longitudinally between the upper surface and the lower surface of the interposer; and
metal that extends longitudinally between the upper surface and the lower surface of the interposer, the metal comprising an upper portion adjacent the upper surface of the interposer, a lower portion adjacent the lower surface of the interposer, and a middle portion between the upper and lower portions;
wherein the metal of the upper portion extends along a first surface of the one or more sidewalls, but does not extend along a second surface of the one or more sidewalls, the second surface being opposite the first surface; and
wherein the metal of the lower portion extends along the second surface of the one or more sidewalls, but does not extend along the first surface of the one or more sidewalls.
18. The semiconductor device of claim 17 , wherein the metal fills the middle portion of each via hole.
19. The semiconductor device of claim 17 , wherein:
a polysilicon fills a first region of the upper portion, the first region spanning between the metal along the first surface of the one or more sidewalls and the second surface of the one or more sidewalls; and
the polysilicon fills a second region of the lower portion, the first region spanning between the metal along the second surface of the one or more sidewalls and the first surface of the one or more sidewalls.
20. The method of claim 9 , wherein said removing the metal from the upper portion and said removing the metal from the lower portion comprises removing the metal from the dielectric layer.