Patent Assignment
Reel/Frame 054046/0673
Assignment of Assignor's Interest
Recorded: 2020-10-12
Pages: 54
Assignor
AMKOR TECHNOLOGY, INC.
Executed: 2019-11-19
Assignee
AMKOR TECHNOLOGY SINGAPORE HOLDING PTE.LTD.
491 B RIVER VALLEY ROAD, #15-02/04, VALLEY POINT, 248373, SINGAPORE
Covered Properties
(408)
Method for making an integrated circuit substrate having laminated laser-embedded circuit layers
Patent:
8,826,531 →
Application:
11/098,995 →
Semiconductor Package in Package
Patent:
9,466,545 →
Application:
11/677,506 →
High Density Memory Card Using Folded Flex
Patent:
9,367,712 →
Application:
11/681,121 →
Stacked Inverted Flip Chip Package and Fabrication Method
Patent:
8,836,115 →
Application:
12/183,778 →
Leadframe Structure for Concentrated Photovoltaic Receiver Package
Patent:
8,680,656 →
Application:
12/348,853 →
Extended Landing Pad Substrate Package Structure and Method
Patent:
8,872,329 →
Application:
12/351,596 →
Semiconductor Device with Increased I/O Leadframe Including Power Bars
Patent:
8,575,742 →
Application:
12/419,180 →
Stackable Protruding via Package and Method
Patent:
8,623,753 →
Application:
12/474,009 →
Frame Interconnect for Concentrated Photovoltaic Module
Patent:
8,866,004 →
Application:
12/481,512 →
Routable Single Layer Substrate and Semiconductor Package Including Same
Patent:
8,551,820 →
Application:
12/568,041 →
Fan Out Build Up Substrate Stackable Package and Method
Patent:
8,796,561 →
Application:
12/573,466 →
Concentrated Photovoltaic Receiver Package with Built-in Connector
Patent:
8,841,547 →
Application:
12/577,064 →
Through Wafer via Structures for Concentrated Photovoltaic Cells
Patent:
8,866,002 →
Application:
12/626,512 →
Thin Stackable Package and Method
Patent:
8,937,381 →
Application:
12/630,586 →
Method of Forming a Plurality of Electronic Component Packages
Patent:
9,691,734 →
Application:
12/632,170 →
Trace Stacking Structure and Method
Patent:
9,230,883 →
Application:
12/690,741 →
Semiconductor Device Having Conductive Pads to Prevent Solder Reflow
Patent:
8,604,625 →
Application:
12/708,432 →
Semiconductor Device and Fabricating Method Thereof
Patent:
8,618,658 →
Application:
12/727,608 →
Semiconductor Package Thermal Tape Window Frame for Heat Sink Attachment
Patent:
8,564,114 →
Application:
12/730,062 →
Shielded Electronic Component Package and Method
Patent:
8,946,886 →
Application:
12/779,784 →
Blind via Capture Pad Structure Fabrication Method
Patent:
8,671,565 →
Application:
12/800,757 →
Concentrated Photovoltaic Receiver Module with Improved Optical Light Guide Assembly
Patent:
9,362,437 →
Application:
12/815,260 →
Molded Light Guide for Concentrated Photovoltaic Receiver Module
Patent:
8,809,677 →
Application:
12/830,138 →
Top Port Mems Microphone Package and Method
Patent:
9,420,378 →
Application:
12/834,682 →
Fingerprint Sensor Package and Method
Patent:
8,717,775 →
Application:
12/848,833 →
Conductive Paste and Mold for Electrical Connection of Photovoltaic Die to Substrate
Patent:
8,552,517 →
Application:
12/881,905 →
Low Stress Substrate and Formation Method
Patent:
8,969,192 →
Application:
12/913,376 →
Shielded Trace Structure and Fabrication Method
Patent:
9,060,430 →
Application:
12/924,918 →
Wafer Level Fan Out Semiconductor Device and Manufacturing Method Thereof
Patent:
9,748,154 →
Application:
12/939,588 →
Electronic Assembly Having Increased Standoff Height
Patent:
8,604,356 →
Application:
12/945,464 →
Magnetic Field Simulator for Testing Singulated or Multi-Site Strip Semiconductor Device and Method Therefor
Integrated Passive Device Structure and Method
Patent:
8,791,501 →
Application:
12/959,851 →
Semiconductor Device Having Overlapped via Apertures
Patent:
8,557,629 →
Application:
12/959,911 →
Semiconductor Device Including Leadframe with Downsets
Patent:
8,674,485 →
Application:
12/963,431 →
Wafers Including Patterned Back Side Layers Thereon
Semiconductor Device Including Leadframe with a Combination of Leads and Lands
Patent:
8,648,450 →
Application:
13/015,071 →
Semiconductor Device
Patent:
9,159,625 →
Application:
13/015,445 →
Top Port with Interposer Mems Microphone Package and Method
Patent:
8,618,619 →
Application:
13/016,343 →
Semiconductor Device with Micro Electromechanical System Die
Patent:
8,921,955 →
Application:
13/034,517 →
Stacked and Staggered Die Mems Package and Method
Patent:
9,013,011 →
Application:
13/046,071 →
Semiconductor Package with Patterning layer and Method of Making Same
Patent:
8,729,710 →
Application:
13/094,728 →
Conformal Shield on Punch Qfn Semiconductor Package
Patent:
8,729,682 →
Application:
13/099,680 →
Integrated Shield Package and Method
Patent:
10,109,591 →
Application:
13/169,385 →
Semiconductor Device with Increased I/O Leadframe
Patent:
8,823,152 →
Application:
13/181,248 →
Electronic Component Package Fabrication Method and Structure
Patent:
8,653,674 →
Application:
13/233,606 →
Underfill Contacting Stacking Balls Package Fabrication Method and Structure
Patent:
8,633,598 →
Application:
13/236,916 →
Package in Package Device for Rf Transceiver Module
Patent:
8,558,365 →
Application:
13/246,564 →
Semiconductor Device with Increased I/O Configuration
Patent:
8,866,278 →
Application:
13/270,000 →
Molded Cavity Substrate Mems Package Fabrication Method and Structure
Patent:
9,029,962 →
Application:
13/272,096 →
Semiconductor Device and Manufacturing Method Thereof
Patent:
9,123,543 →
Application:
13/274,877 →
Wafer Level Chip Scale Package and Method of Fabricating Wafer Level Chip Scale Package
Patent:
8,828,802 →
Application:
13/286,903 →
Wafer Level Fan Out Package
Patent:
8,552,556 →
Application:
13/302,501 →
Conductive Pad on Protruding Through Electrode Semiconductor Device
Patent:
8,552,548 →
Application:
13/306,685 →
Electronic Component Package Fabrication Method and Structure
Patent:
8,552,557 →
Application:
13/327,440 →
Reversible Top/Bottom Mems Package
Molded Image Sensor Package and Method
Shielding Technique for Semiconductor Package Including Metal Lid and Metalized Contact Area
Patent:
9,153,543 →
Application:
13/356,330 →
Shielding Technique for Semiconductor Package Including Metal Lid
Patent:
9,362,209 →
Application:
13/356,349 →
Methods and Structures for Increasing the Allowable Die Size in Tmv Packages
Patent:
9,721,872 →
Application:
13/398,646 →
Electronic Component Package Having Bleed Channel Structure and Method
Patent:
8,982,577 →
Application:
13/399,321 →
Semiconductor Device with Leadframe Configured to Facilitate Reduced Burr Formation
Patent:
9,704,725 →
Application:
13/412,848 →
Packaging for Fingerprint Sensors and Methods of Manufacture
Embedded Component Package and Fabrication Method
Patent:
9,129,943 →
Application:
13/434,181 →
Backside Warpage Control Structure and Fabrication Method
Patent:
9,048,298 →
Application:
13/434,217 →
Electronic Component Package Fabrication Method and Structure
Patent:
8,664,090 →
Application:
13/447,650 →
Warpage Control Stiffener Ring Package and Fabrication Method
Patent:
8,986,806 →
Application:
13/452,006 →
Integrated Circuit with Efficient Mems Architecture
Patent:
9,061,884 →
Application:
13/454,881 →
Semiconductor Device
Electrical Circuit with Component-Accommodating Lid
Patent:
8,786,075 →
Application:
13/458,353 →
Wire Fence Fingerprint Sensor Package and Fabrication Method
Patent:
9,025,301 →
Application:
13/459,661 →
Lead Frame for Semiconductor Device
Shield Lid Interconnect Package and Method
Patent:
9,433,117 →
Application:
13/475,469 →
Ic Package with Integrated Electrostatic Discharge Protection
Patent:
8,633,575 →
Application:
13/479,829 →
Stacked Redistribution Layer (Rdl) Die Assembly Package
Patent:
8,629,546 →
Application:
13/487,705 →
Stackable via Package and Method
Patent:
8,704,368 →
Application:
13/528,206 →
Die Seal Design and Method and Apparatus for Integrated Circuit Production
Patent:
8,940,587 →
Application:
13/546,870 →
Design and Method for Controlling Molding Compound Geometry Around a Semiconductor Die
Patent:
8,912,051 →
Application:
13/564,567 →
Semiconductor Device
Semiconductor Device
Mushroom Shaped Bump on Repassivation
Patent:
8,946,891 →
Application:
13/603,039 →
PROCESSING SOLDERBRACE USING LIGHT WAVELENGTH FILTER AND A BROADBAND LIGHT SOURCE (As amended)
Patent:
8,941,050 →
Application:
13/608,521 →
Merged Fiducial for Semiconductor Chip Packages
Patent:
9,041,229 →
Application:
13/608,544 →
Molded Electronic Package Geometry to Control Warpage and Die Stress
Patent:
9,269,872 →
Application:
13/614,631 →
Electronic Package With Embedded Materials in a Molded Structure to Control Warpage and Stress
Patent:
9,349,613 →
Application:
13/614,648 →
Integrated Circuit Package and Method of Making the Same
Patent:
8,853,836 →
Application:
13/662,702 →
Method and System for Solder Shielding of Ball Grid Arrays
Patent:
9,337,137 →
Application:
13/663,001 →
Through via Nub Reveal Method and Structure
Patent:
9,324,614 →
Application:
13/663,208 →
Method And System For A Semiconductor Device Package With A Die-To-Die First Bond
Methods for Temporary Wafer Molding for Chip-on-Wafer Assembly
Method And System For A Semiconductor Device Package With A Die To Interposer Wafer First Bond
Method and System for a Semiconductor for Device Package with a Die-to-Packaging Substrate First Bond
Buildup Dielectric Layer Having Metallization Pattern Semiconductor Package Fabrication Method
Patent:
9,691,635 →
Application:
13/679,627 →
Mechanical Tape Separation Package
Patent:
8,753,730 →
Application:
13/680,687 →
Method And System For Backside Dielectric Patterning For Wafer Warpage And Stress Control
Patent:
8,987,050 →
Application:
13/690,817 →
Semiconductor Package with Alternating Thermal Interface and Adhesive Materials and Method for Manufacturing the Same
Semiconductor Device and Manufacturing Method Thereof
Shielded Package Having Shield Lid
Patent:
8,552,539 →
Application:
13/737,325 →
Semiconductor Device and Manufacturing Method Thereof
Patent:
9,524,906 →
Application:
13/738,669 →
Semiconductor Package and Method for Manufacturing the Same
Semiconductor Package and Manufacturing Method Thereof
Method of Forming a Thin Substrate Chip Scale Package Device and Structure
Electronic Package Structure with Insulated Adhesion Portion for Affixing and Isolating Lands Spaced Apart from Land Connect Bar Within a Leadframe
Through via Recessed Reveal Structure and Method
Patent:
9,082,833 →
Application:
13/756,167 →
Semiconductor Device and Manufacturing Method Thereof
Leadframe and Semiconductor Package Made Using the Leadframe
Flip Chip Bump Structure and Fabrication Method
Patent:
8,704,369 →
Application:
13/765,152 →
Electronic Component Package Fabrication Method and Structure
Patent:
9,245,862 →
Application:
13/765,388 →
Mems Package with Mems Die, Magnet, and Window Substrate Fabrication Method and Structure
Patent:
9,758,372 →
Application:
13/766,171 →
Microfluidics Sensor Package Fabrication Method and Structure
Patent:
9,670,445 →
Application:
13/793,541 →
Molded Semiconductor Package with Snap Lid
Through via Connected Backside Embedded Circuit Features Structure and Method
Patent:
9,159,672 →
Application:
13/861,711 →
Semiconductor Device and Manufacturing Method Thereof
Methods for Temporary Bussing of Semiconductor Package Substrates
Patent:
9,449,890 →
Application:
13/892,118 →
Semiconductor Device with Metal Dam and Fabricating Method
Patent:
10,242,956 →
Application:
13/894,403 →
Stackable Variable Height via Package and Method
Patent:
10,257,942 →
Application:
13/896,710 →
Method of Making a Semiconductor Device
Robust Pillar Structure for Semicondcutor Device Contacts
Patent:
9,484,291 →
Application:
13/903,468 →
Stackable Package and Method
Patent:
9,496,210 →
Application:
13/912,540 →
Wafer Level Package and Fabrication Method
Patent:
8,691,632 →
Application:
13/918,307 →
Semiconductor Device and Manufacturing Method Thereof
Patent:
8,900,995 →
Application:
13/927,964 →
Semiconductor Package and Manufacturing Method Thereof
Lead Frame Package Having Discharge Holes and Method of Manufacturing the Same
Semiconductor Package with Improved Redistribution Layer Design and Fabricating Method Thereof
Semiconductor Package and Manufacturing Method Thereof
Wafer Level Fan-Out Package with a Fiducial Die
Fine Pitch Copper Pillar Package and Method
Patent:
9,462,690 →
Application:
13/963,635 →
Metal Mesh Lid Mems Package and Method
Patent:
9,162,871 →
Application:
13/969,052 →
Exposed Die Overmolded Flip Chip Package and Fabrication Method
Patent:
8,847,372 →
Application:
13/972,292 →
Plating Structure For Wafer Level Packages
Semiconductor Package Having a Plurality of Input/Output Members
Patent:
9,117,684 →
Application:
13/974,443 →
Conductive Pad on Protruding Through Electrode Semiconductor Device
Patent:
8,981,572 →
Application:
14/017,797 →
Fan-Out Semiconductor Package
Patent:
9,214,434 →
Application:
14/017,802 →
Wafer Level Package and Fabrication Method
Patent:
8,710,649 →
Application:
14/019,136 →
Shielded Package Having Shield Lid
Patent:
9,123,718 →
Application:
14/021,604 →
Semiconductor Device Having Overlapped via Apertures
Patent:
9,177,932 →
Application:
14/028,290 →
Semiconductor Device Utilzing Redistribution Layers to Couple Stacked Die
Semiconductor Device with Plated Conductive Pillar Coupling
Application:
14/063,829 →
Publication:
US 2015/0021767
Semiconductor Device with Plated Pillars and Leads
Apparatus and Method for Testing Sound Transducers
Embedded Vibration Management System
Patent:
10,032,726 →
Application:
14/069,814 →
Land Structure for Semiconductor Package and Method Therefor
Embedded Die in Panel Method and Structure
Patent:
9,576,917 →
Application:
14/082,333 →
Stress Relieving Through-Silicon Vias
Patent:
9,607,890 →
Application:
14/082,422 →
Package of Finger Print Sensor and Fabricating Method Thereof
Semicondutor Device with Through-Silicon via-Less Deep Wells
Semiconductor Device Using Emc Wafer Support System and Fabricating Method Thereof
Semiconductor Device
Semiconductor Device Having Conductive Pads with Neck-Down Portions to Prevent Solder Reflow
Patent:
9,171,812 →
Application:
14/088,882 →
Electronic Device Package Structure and Method of Fabricating the Same
Semiconductor Device Including Leadframe with a Combination of Leads and Lands and Method
Patent:
9,275,939 →
Application:
14/106,139 →
Integrated Circuit Package and Method of Making the Same
Patent:
8,963,301 →
Application:
14/142,457 →
Column and Stacking Balls Package Fabrication Method and Structure
Patent:
8,890,337 →
Application:
14/152,035 →
Semiconductor Device Package Formed in a Chip-on-Wafer Last Process Using Thin Film Adhesives
Patent:
9,437,575 →
Application:
14/159,237 →
Thin Sandwich Embedded Package
Application:
14/172,611 →
Publication:
US 2015/0221570
Thin Bonded Interposer Package
Patent:
9,711,485 →
Application:
14/172,889 →
Electronic Component Package Fabrication Method and Structure
Patent:
8,941,250 →
Application:
14/182,083 →
Semiconductor Device and Manufacturing Method Thereof
Semiconductor Device and Manufacturing Method Thereof
Stackable via Package and Method
Patent:
9,012,789 →
Application:
14/246,286 →
Singulated Unit Substrate for a Semicondcutor Device
Application:
14/255,726 →
Publication:
US 2015/0303170
Flip Chip Self-Alignment Features for Substrate and Leadframe Applications
Patent:
10,032,699 →
Application:
14/264,027 →
Wafer Level Package and Fabrication Method
Patent:
8,952,522 →
Application:
14/264,970 →
Micro Lead Frame Structure Having Reinforcing Portions and Method
Copper Pillar Sidewall Protection
Semiconductor Device and Manufacturing Method Thereof
Semiconductor Device and Manufacturing Method Thereof
Semiconductor Device with Redistribution Layers on Partial Encapsulation and Non-Photosensitive Passivation Layers
Semiconductor Package Lid Thermal Interface Material Standoffs
Patent:
9,892,990 →
Application:
14/339,633 →
Semiconductor Device with Thin Redistribution Layers
Semiconductor Package Structure for Improving Die Warpage and Manufacturing Method Thereof
Semiconductor Device with Redistribution Layers Formed Utilizing Dummy Substrates
Semiconductor Package with Reduced Thickness
Application:
14/452,933 →
Publication:
US 2015/0041980
Microfluidic Sensor Package Structure and Method
Semiconductor Package and Fabricating Method Thereof
Manufacturing Method of Semiconductor Device and Semiconductor Device Manufactured Thereby
Semiconductor Device with a Semiconductor Die Embedded Between an Extended Substrate and a Bottom Substrate
Extended Landing Pad Substrate Package Structure and Method
Patent:
9,462,704 →
Application:
14/517,403 →
Semiconductor Package and Method Therefor
Semiconductor Device with Embedded Semiconductor Die and Substrate-to-Substrate Interconnects
Semiconductor Device with Reduced Thickness
Interposer, Manufacturing Method Thereof, Semiconductor Package Using the Same, and Method for Fabricating the Semiconductor Package
Semiconductor Package Structure and Manufacturing Method Thereof
Application:
14/538,018 →
Publication:
US 2015/0130054
Web-Enabled Conferencing and Meeting Implementations with a Subscription-Based Model
Patent:
9,881,282 →
Application:
14/562,862 →
Semiconductor Device
Encapsulated Semiconductor Package
Patent:
10,461,006 →
Application:
14/581,305 →
Encapsulated Semiconductor Package
Patent:
9,812,386 →
Application:
14/581,556 →
Wafer Level Package and Fabrication Method
Patent:
9,054,117 →
Application:
14/586,263 →
Laser Assisted Bonding for Semiconductor Die Interconnections
Integrated Circuit Package and Method of Making the Same
Patent:
9,224,676 →
Application:
14/592,648 →
Semiconductor Device Having Single Layer Substrate and Method
Embedded Trace Substrate and Method of Forming the Same
Conductive Pad on Protruding Through Electrode
Patent:
9,431,323 →
Application:
14/615,127 →
Stackable via Package and Method
Patent:
9,730,327 →
Application:
14/657,032 →
Reversible Top/Bottom Mems Package
Semiconductor Device and Manufacturing Method Thereof
Semiconductor Package with High Routing Density Patch
Manufacturing Method of Semiconductor Device and Semiconductor Device Thereof
Semiconductor Package and Fabricating Method Thereof
Semiconductor Device Package and Manufacturing Method Thereof
Patent:
9,349,681 →
Application:
14/698,188 →
Semiconductor Device Package and Manufacturing Method Thereof
Patent:
9,966,300 →
Application:
14/698,634 →
Molded Cavity Substrate Mems Package Fabrication Method and Structure
Patent:
9,346,668 →
Application:
14/710,361 →
Semiconductor Device and Manufacturing Method Thereof
Lead Frame Package Having Discharge Hole and Method of Manufacturing the Same
Semiconductor Package with Semiconductor Die Directly Attached to Lead Frame and Method
Semiconductor Device Utilizing Redistribution Layers To Couple Stacked Die
Wafer Level Package and Fabrication Method
Patent:
9,406,645 →
Application:
14/734,192 →
Semiconductor Package And Manufacturing Method Thereof
Application:
14/739,345 →
Publication:
US 2015/0274511
Semiconductor Device Redistribution Layer with Narrow Trace Width Relative to Passivation Layer Opening
Semiconductor Package and Manufacturing Method Thereof
Package of Finger Print Sensor and Fabricating Method Thereof
Method of Manufacturing a Semiconductor Device
Semiconductor Package and Fabricating Method Thereof
Patent:
9,543,242 →
Application:
14/823,689 →
Method of Manufacturing a Package-on-Package Type Semiconductor Package
Method of Manufacturing a Semiconductor Device and Interconnection Structures Thereof
Micro Lead Frame Structure Having Reinforcing Portions and Method
Embedded Component Package and Fabrication Method
Patent:
10,014,240 →
Application:
14/846,543 →
Semiconductor Package and Method Therefor
Stacked Semiconductor Package and Manufacturing Method Thereof
Semiconductor Device Having Overlapped via Apertures
Patent:
9,837,331 →
Application:
14/924,994 →
Wafer-Level Stack Chip Package and Method of Manufacturing the Same
Packaged Electronic Device Having Integrated Antenna and Locking Structure
Semiconductor Device and Manufacturing Method Thereof
Application:
14/935,912 →
Publication:
US 2017/0133334
Encapsulated Semiconductor Package and Method of Manufacturing Thereof
Transient Interface Gradient Bonding for Metal Bonds
Wafer Level Fan Out Package and Method of Fabricating Wafer Level Fan Out Package
Patent:
10,224,217 →
Application:
14/965,617 →
Packaged Electronic Device Having Reduced Parasitic Effects and Method
Semiconductor Device and Manufacturing Method Thereof
Semiconductor Device and Manufacturing Method Thereof
Semiconductor Device Including Leadframe with a Combination of Leads and Lands and Method
Patent:
9,508,631 →
Application:
14/983,937 →
Electronic Package Structure Having Insulated Substrate with Lands and Conductive Patterns
Chip-Scale Electronic Package Structure with Conductive Connective Element Having Increased Surface Area and Laterally Spaced Connection Points for Improved Connectivity
Trace Stacking Structure and Method
Patent:
10,128,194 →
Application:
14/988,563 →
Semiconductor Product with Interlocking Metal-to-Metal Bonds and Method for Manufacturing Thereof
Patent:
9,559,075 →
Application:
14/989,455 →
Semiconductor Device and Manufacturing Method Thereof
Application:
14/995,806 →
Publication:
US 2016/0211221
Semiconductor Package Using a Contact in a Pleated Sidewall Encapsulant Opening
Semiconductor Package Using a Coreless Signal Distribution Structure
Semiconductor Device and Manufacturing Method Thereof
Land Structure for Semiconductor Package and Method Therefor
Semiconductor Package and Manufacturing Method Thereof
Molded Electronic Package Geometry To Control Warpage And Die Stress
Application:
15/051,216 →
Publication:
US 2016/0172214
Semiconductor Package and Manufacturing Method Thereof
Electronic Device with a Plurality of Redistribution Structures Having Different Respective Sizes
Semiconductor Device and Manufacturing Method Thereof
Semiconductor Device with Redistribution Layers on Partial Encapsulation and Non-Photosensitive Passivation Layers
Semiconductor Device and Manufacturing Method Thereof
Semiconductor Device and Manufacturing Method Thereof
Electronic Device with Interconnection Structure Oblate Ellipsoid-Shaped Aperture
Finger Print Sensor and Manufacturing Method Thereof
System and Method for Laser Assisted Bonding of Semiconductor Die
Fingerprint Sensor and Manufacturing Method Thereof
Method of Forming a Semiconductor Package with Conductive Interconnect Frame and Structure
Method and Apparatus for Distributing Sensor Data
Molded Semiconductor Package
Fingerprint Sensor and Manufacturing Method Thereof
Semiconductor Device Utilizing an Adhesive to Attach an Upper Package to a Lower Die
Semiconductor Device and Manufacturing Method Thereof
Method for Fabricating Semiconductor Package and Semiconductor Package Using the Same
Patent:
9,613,829 →
Application:
15/148,895 →
Semiconductor Device and Manufacturing Method Thereof
Application:
15/149,038 →
Publication:
US 2017/0200686
Capacitor of Semiconductor Integrated Circuit and Method for Manufacturing the Same
Application:
15/149,054 →
Publication:
US 2017/0200782
Semiconductor Package and Manufacturing Method Thereof
Semiconductor Package and Manufacturing Method Thereof
Semiconductor Device and Manufacturing Method Thereof
Semiconductor Device and Manufacturing Method Thereof
Application:
15/149,158 →
Publication:
US 2016/0379915
Method of Forming a Semiconductor Device Including Forming an Electromagnetic Interference (Emi) Shield Layer Over an Encapsulated Die on an Adhesive Tape
Application:
15/149,378 →
Publication:
US 2017/0141046
Semiconductor Package Having an Etched Groove for an Embedded Device Formed on Bottom Surface of a Support Substrate and a Method for Fabricating the Same
Application:
15/149,436 →
Publication:
US 2017/0194239
Semiconductor Package and Manufacturing Method Thereof
Semiconductor Device Package and Manufacturing Method Thereof
Patent:
9,553,041 →
Application:
15/162,424 →
Semiconductor Device and Manufacturing Method Thereof
Method for Fabricating Semiconductor Package Having a Multi-Layer Encapsulated Conductive Substrate and Structure
Semiconductor Package Having Routable Encapsulated Conductive Substrate and Method
Reversible Top/Bottom MEMS Package
Semiconductor Package Including Premold and Method of Manufacturing the Same
Application:
15/202,245 →
Publication:
US 2016/0343593
Semiconductor Package and Fabricating Method Thereof
Patent:
9,653,428 →
Application:
15/207,186 →
Semiconductor Device and Manufacturing Method Thereof
Semiconductor Package with Clip Alignment Notch
Semiconductor Package and Manufacturing Method Thereof
Top Port Mems Package and Method
Patent:
10,327,076 →
Application:
15/214,567 →
Semiconductor Device and Manufacturing Method Thereof
Semiconductor Device and Manufacturing Method Thereof
Wafer Level Package and Fabrication Method
Patent:
9,871,015 →
Application:
15/225,284 →
Packaging for Fingerprint Sensors and Methods of Manufacture
Method and System for Packing Optimization of Semiconductor Devices
Application:
15/233,271 →
Publication:
US 2018/0047692
Shielded Electronic Component Package
Method of manufacturing a semiconductor package
Method of Manufacturing an Electronic Device and Electronic Device Manufactured Thereby
Semiconductor Device Comprising a Conductive Pad on a Protruding-Through Electrode
Patent:
9,947,623 →
Application:
15/250,397 →
Semiconductor Device and Manufacturing Method Thereof
Semiconductor Device and Manufacturing Method
Patent:
9,978,644 →
Application:
15/258,001 →
Semiconductor Package in Package
Fine Pitch Copper Pillar Package and Method
Patent:
10,224,270 →
Application:
15/284,242 →
Robust Pillar Structure for Semiconductor Device Contacts
Patent:
10,236,268 →
Application:
15/285,110 →
Semiconductor Package and Manufacturing Method Thereof
Semiconductor Device Including Leadframe with a Combination of Leads and Lands and Method
Patent:
9,631,481 →
Application:
15/293,524 →
Semiconductor Package and Manufacturing Method Thereof
Semiconductor Device and Manufacturing Method Thereof
Manufacturing Method of Semiconductor Device and Semiconductor Device Thereof
Stackable Package and Method
Patent:
12,009,343 →
Application:
15/347,545 →
Semiconductor Device and Method of Manufacturing Thereof
Semiconductor Device and Manufacturing Method Thereof
Application:
15/351,026 →
Publication:
US 2018/0134546
Semiconductor Device with Embedded Semiconductor Die and Substrate-to-Substrate Interconnects
Semiconductor Device Having Conductive Wire with Increased Attachment Angle and Method
Semiconductor Device and Method of Manufacturing Thereof
Semiconductor Device and Manufacturing Method Thereof
Patent:
10,483,222 →
Application:
15/383,923 →
Semiconductor Product with Interlocking Metal-to-Metal Bonds and Method for Manufacturing Thereof
Semiconductor Device and Manufacturing Method Thereof
Embedded Die in Panel Method and Structure
Application:
15/398,845 →
Publication:
US 2017/0278810
Semiconductor Package and Fabricating Method Thereof
Semiconductor Package With EMI Shield and Fabricating Method Thereof
Semiconductor Device Package and Manufacturing Method Thereof
Semiconductor Device Having an Encapsulated Front Side and Interposer and Manufacturing Method Thereof
Semiconductor Device Having Stacked Dies and Stacked Pillars and Method of Manufacturing Thereof
Semiconductor Package and Fabricating Method Thereof
Patent:
10,037,949 →
Application:
15/447,831 →
Semiconductor Package with Multiple Compartments
Patent:
9,932,221 →
Application:
15/448,177 →
Semiconductor Device Including Leadframe with a Combination of Leads and Lands and Method
Patent:
9,978,695 →
Application:
15/457,937 →
Method of Forming a Packaged Semiconductor Device Using Ganged Conductive Connective Assembly and Structure
Semiconductor Device and Method of Manufacturing Thereof
Semiconductor Device with Tiered Pillar and Manufacturing Method Thereof
Stress Relieving Through-Silicon Vias
Patent:
10,134,635 →
Application:
15/468,433 →
Semiconductor Device and Method of Manufacturing Thereof
Semiconductor Device with Thin Redistribution Layers
Method for Fabricating Semiconductor Package and Semiconductor Package Using the Same
Semiconductor Device with Leadframe Configured to Facilitate Reduced Burr Formation
Patent:
10,090,228 →
Application:
15/479,223 →
Semiconductor Device and Manufacturing Method Thereof
Semiconductor Device Using Emc Wafer Support System and Fabricating Method Thereof
Fingerprint Sensor and Manufacturing Method Thereof
Semiconductor Package and Fabricating Method Thereof
Semiconductor Package Having Inspection Structure and Related Methods
Semiconductor Device Having Emi Shielding Structure and Related Methods
Application:
15/632,335 →
Publication:
US 2018/0374798
Encapsulated Semiconductor Package
Patent:
11,094,560 →
Application:
15/634,041 →
Method of Forming a Plurality of Electronic Component Packages
Packaging for Fingerprint Sensors and Methods of Manufacture
Patent:
47,890 →
Application:
15/646,973 →
Thin Bonded Interposer Package
Patent:
10,242,966 →
Application:
15/650,205 →
Wafer Level Fan Out Semiconductor Device and Manufacturing Method Thereof
Methods and Structures for Increasing the Allowable Die Size in Tmv Packages
Patent:
10,347,562 →
Application:
15/663,024 →
Fingerprint Sensor and Manufacturing Method Thereof
Stackable via Package and Method
Patent:
10,034,372 →
Application:
15/670,908 →
Method of Manufacturing an Electronic Device and Electronic Device Manufactured Thereby
Method of Manufacturing a Package-on-Package Type Semiconductor Package
Encapsulated Semiconductor Package and Method of Manufacturing Thereof
Semiconductor Package Using A Coreless Signal Distribution Structure
Packaging for Fingerprint Sensors and Methods of Manufacture
Method of Forming a Packaged Semiconductor Device Having Enhanced Wettable Flank and Structure
Patent:
10,199,312 →
Application:
15/700,101 →
Packaged Electronic Device Having Stepped Conductive Structure and Related Methods
Semiconductor Package and Fabricating Method Thereof
Electronic Device with Top Side Pin Array and Manufacturing Method Thereof
Heat Sink Attached to an Electronic Component in a Packaged Device
Semiconductor Package and Manufacturing Method Thereof
Semiconductor Device with Redistribution Layers on Partial Encapsulation and Non-Photosensitive Passivation Layers
Semiconductor Device with Thin Redistribution Layers
Semiconductor Device and Manufacturing Method Thereof
Semiconductor Device and Manufacturing Method Thereof
Land Structure for Semiconductor Package and Method Therefor
Electronic Device Package and Fabricating Method Thereof
Manufacturing Method of Semiconductor Device and Semiconductor Device Thereof
Semiconductor Package and Fabricating Method Thereof
Semiconductor Device and Manufacturing Method Thereof
Semiconductor Device and Method of Manufacturing a Semiconductor Device
Patent:
10,134,687 →
Application:
15/841,892 →
Semiconductor Device with Integrated Heat Distribution and Manufacturing Method Thereof
Semiconductor Device and Manufacturing Method Thereof
Semiconductor Package and Fabricating Method Thereof
Method of Manufacturing a Semiconductor Device
Semiconductor Package and Manufacturing Method Thereof
Wafer Level Package and Fabrication Method
Patent:
10,665,567 →
Application:
15/872,397 →
Method for Fabricating Semiconductor Package and Semiconductor Package Using the Same
Method of Forming a Molded Substrate Electronic Package and Structure
Electronic Package Structure with Improved Board Level Reliability
Method of Manufacturing an Electronic Device and Electronic Device Manufactured Thereby
Method of Forming an Electronic Device Structure Having an Electronic Component with an on-Edge Orientation and Related Structures
Packaged Electronic Device Having Integrated Antenna and Locking Structure
System and Method for Laser Assisted Bonding of Semiconductor Die
Semiconductor Package Structure for Improving Die Warpage and Manufacturing Method Thereof
Semiconductor Package with Multiple Compartments
Semiconductor Package and Manufacturing Method Thereof
Electronic Device with Adaptive Vertical Interconnect and Fabricating Method Thereof
Embedded Ball Land Substrate, Semiconductor Package, and Manufacturing Methods
Semiconductor Device and Manufacturing Method Thereof
Semiconductor Device with Optically-Transmissive Layer and Manufacturing Method Thereof
Electronic device comprising a conductive pad on a protruding-through electrode
Patent:
10,410,967 →
Application:
15/953,024 →
Semiconductor Package Using Cavity Substrate and Manufacturing Methods
Method and System for Packing Optimization of Semiconductor Devices
Semiconductor Device Package and Manufacturing Method Thereof
Patent:
10,283,400 →
Application:
15/973,329 →
Semiconductor Device and Manufacturing Method Thereof
Sensor Package and Manufacturing Method Thereof
Semiconductor Device and Manufacturing Method Thereof
Semiconductor Device with Through-Mold Via
Semiconductor Package Having Routable Encapsulated Conductive Substrate and Method
Semiconductor Device and Method of Manufacturing Thereof
Semiconductor Package and Manufacturing Method Thereof
Stackable via Package and Method
Patent:
10,206,285 →
Application:
16/042,312 →
Flip Chip Self-Alignment Features for Substrate and Leadframe Applications
Semiconductor Package and Manufacturing Method Thereof
Semiconductor Device Having Upper and Lower Redistribution Layers
Method of Forming a Packaged Semiconductor Device Using Ganged Conductive Connective Assembly and Structure
Semiconductor Device and Method of Manufacturing Thereof
Manufacturing Method of Semiconductor Device and Semiconductor Device Thereof
Semiconductor Device and Manufacturing Method Thereof
Semiconductor Device with Improved Thermal Dissipation and Manufacturing Methods
Semiconductor Package with High Routing Density Patch
Semiconductor Device and Manufacturing Method Thereof
Semiconductor Device with a Semiconductor Die Embedded Between an Extended Substrate and a Bottom Substrate
Semiconductor Device Having Conductive Wire with Increased Attachment Angle and Method
Integrated Shield Package and Method
Semiconductor Device and Method of Manufacturing a Semiconductor Device
Semiconductor Device and a Method of Manufacturing a Semiconductor Device
Semiconductor Package and Fabricating Method Thereof
Semiconductor Device Having a Lid Configured as an Enclosure and a Capacitive Structure and Method of Manufacturing a Semiconductor Device
Method of Forming a Packaged Semiconductor Device Having Enhanced Wettable Flank and Structure
Semiconductor Package Having Inspection Structure and Related Methods
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