Method of manufacturing a semiconductor device and interconnection structures thereof

1. A method of manufacturing a semiconductor package, the method comprising:

forming a dielectric layer on a semiconductor die, where the semiconductor die comprises a die pad;

forming a conductive layer on the dielectric layer, wherein the conductive layer is electrically connected to the die pad through an opening in the dielectric layer;

forming a first temporary structure on the conductive layer;

forming a mold material to contact at least a respective portion of each of the dielectric layer, the conductive layer and the first temporary structure;

thinning the mold material and the first temporary structure;

removing the first temporary structure from the mold material; and

forming an interconnection structure in a cavity in the mold material created by said removing the first temporary structure.

2. The method of claim 1 , wherein the first temporary structure comprises a photoresist material and/or a dry film material.

3. The method of claim 1 , wherein:

the first temporary structure comprises a top surface, a bottom surface coupled to the conductive layer, and a plurality of side surfaces; and

at least one of the side surfaces of the interconnection structure is planar and has a non-zero and finite slope.

4. The method of claim 3 , wherein each of the plurality of side surfaces of the first temporary structure is planar, and the first temporary structure is shaped like an upside-down pyramid with a truncated apex.

5. The method of claim 1 , wherein said forming the first temporary structure comprises stacking a plurality of layers of increasing lateral dimension.

6. The method of claim 1 comprising:

prior to forming an empty groove in the mold material, forming a second temporary structure on the semiconductor die for singulating the semiconductor package;

removing the second temporary structure from the mold material, thereby creating the empty groove in the mold material; and

singulating the semiconductor package at the empty groove.

7. The method of claim 6 , wherein said removing the second temporary structure is performed simultaneously with said removing the first temporary structure.

8. The method of claim 6 , wherein the first and second temporary structures are formed of a same material in a same process.

9. The method of claim 6 , wherein the semiconductor die comprises a lower passivation layer, different from the dielectric layer, through which the die pad is exposed and on which the dielectric layer is formed.

10. The method of claim 9 , wherein:

said forming the dielectric layer comprises forming the dielectric layer directly on the lower passivation layer;

said forming the conductive layer comprises forming the conductive layer directly on the dielectric layer;

said forming the first temporary structure comprises forming the first temporary structure directly on the conductive layer; and

said forming the second temporary structure comprises forming the second temporary structure directly on the lower passivation layer.

11. The method of claim 1 , comprising:

prior to forming an empty fiducial mark in the mold material, forming a second temporary structure for the fiducial mark; and

removing the second temporary structure from the mold material, thereby forming the empty fiducial mark in the mold material, the fiducial mark different from a cavity for an interconnection structure and different from a singulation groove.

12. The method of claim 11 , wherein said removing the second temporary structure from the mold material is performed simultaneously with said removing the first temporary structure.

13. The method of claim 11 , wherein said forming the second temporary structure comprises forming the second temporary structure within a central area of the semiconductor package surrounded by a plurality of temporary structures for interconnection structures.

14. A method of manufacturing a semiconductor package, the method comprising:

forming a conductive layer over a semiconductor die;

forming a first temporary pattern member for an interconnection structure on the conductive layer, the first temporary structure comprising a first end facing the conductive layer, a second end facing away from the conductive layer, and at least one lateral surface between the first end and the second end;

forming an encapsulating material to cover at least a respective portion of each of the conductive layer, and the at least one lateral surface of the first temporary pattern member;

thinning the encapsulating material and the first temporary pattern member;

removing the first temporary pattern member; and

forming an interconnection structure in a cavity in the encapsulating material created by said removing the first temporary pattern member.

15. The method of claim 14 , wherein the interconnection structure comprises:

a first portion that extends entirely through the encapsulating material and has a linear profile at an interface between the first portion and the encapsulating material; and

a second portion that protrudes from the encapsulating material and has a rounded profile.

16. The method of claim 14 , wherein:

the interconnection structure comprises a top surface, a bottom surface coupled to the conductive layer, and a plurality of side surfaces; and

at least one of the side surfaces of the interconnection structure is planar and has a non-zero and finite slope.

17. The method of claim 14 , comprising prior to said forming the encapsulating material:

forming another temporary pattern member on the semiconductor die for singulating the package and/or for a fiducial, and

removing the another temporary pattern member from the encapsulating material to create an opening in the encapsulating material for singulating the package and/or for a fiducial.

18. A method of manufacturing a semiconductor device, the method comprising:

providing a structure comprising:

a semiconductor die comprising a die pad;

a dielectric layer on the semiconductor die and comprising an opening through which the die pad is exposed; and

a conductive layer on the dielectric layer and electrically connected to the die pad through the opening in the dielectric layer;

forming an encapsulating material to cover at least respective portions of the dielectric layer and the conductive layer, where the encapsulating material comprises a via that extends through the encapsulating material and exposes a portion of the conductive layer; and

forming an interconnection structure comprising:

a first portion that extends through the encapsulating material, is entirely laterally surrounded by the encapsulating material, and has a planar profile with a non-zero and finite slope at an interface between the first portion and the encapsulating material; and

a second portion that protrudes from the encapsulating material and has a rounded profile,

wherein the first portion of the interconnection structure comprises solder.

19. The method of claim 18 , wherein said forming an encapsulating material comprises:

forming a temporary structure on the conductive layer;

forming the encapsulating material to cover at least respective portions of the dielectric layer, the conductive layer, and the temporary structure;

thinning the encapsulating material and the temporary structure; and

removing the temporary structure, thereby forming a cavity in the encapsulating material.

20. The method of claim 18 , wherein the first portion of the interconnection structure comprises at least four planar sides of a same size that contact the encapsulating material.