Buildup dielectric layer having metallization pattern semiconductor package fabrication method

1. A method of manufacturing a semiconductor package, the method comprising:

coupling a semiconductor die and a substrate, wherein:

the substrate comprises: a first substrate side, a second substrate side, and a plurality of perimeter substrate sides extending between the first substrate side and the second substrate side;

the semiconductor die comprises: a first die side, a second die side, and a plurality of perimeter die sides extending between the first die side and the second die side; and

said mounting comprises mounting the second die side to the first substrate side;

encapsulating the semiconductor die and the substrate to form an encapsulation that covers at least the perimeter die sides and the first substrate side, but does not cover the second substrate side, the encapsulation comprising a first encapsulation side facing away from the substrate and a second encapsulation side facing the substrate;

laser-ablating a via hole through at least the encapsulation, the entire via hole extending through only insulative material;

depositing conductive material within the via hole to form a conductive via;

forming a first buildup dielectric layer on the encapsulation;

ablating an artifact in the first buildup dielectric layer, wherein the ablated artifact comprises a channel in the first buildup dielectric layer, the channel extending in a direction parallel to the first substrate side; and

depositing a first metal layer in the ablated artifact to form at least a portion of a first electrically conductive pattern in the first buildup dielectric layer.

2. The method of claim 1 , wherein said depositing a first metal layer in the ablated artifact comprises plating copper in the ablated artifact.

3. The method of claim 1 , wherein the channel extends over the first die side.

4. The method of claim 1 , wherein said forming the first buildup dielectric layer on the encapsulation comprises forming the first buildup dielectric layer on the first encapsulation side.

5. The method of claim 1 , further comprising:

forming a second buildup dielectric layer on the first buildup dielectric layer;

ablating a second artifact in the second buildup dielectric layer; and

depositing a second metal layer in the ablated second artifact to form at least a portion of a second electrically conductive pattern in the second buildup dielectric layer,

wherein the ablated second artifact comprises a channel in the second buildup dielectric layer, the channel extending in a direction parallel to the first substrate side.

6. The method of claim 1 , wherein said laser-ablating a via hole comprises laser-ablating a via hole through the encapsulation and through the substrate to a pad on the second substrate side that covers the via hole, said laser-ablating stopping at a first side of the pad that covers the via hole.

7. A method of manufacturing a semiconductor package, the method comprising:

mounting a semiconductor die on a substrate, wherein:

the substrate comprises: a first substrate side, a second substrate side, and a plurality of perimeter substrate sides extending between the first substrate side and the second substrate side;

the semiconductor die comprises: a first die side, a second die side, and a plurality of perimeter die sides extending between the first die side and the second die side; and

said mounting comprises mounting the second die side on the first substrate side;

covering at least the perimeter die sides and the first substrate side with an encapsulation;

forming an electrically conductive via through the encapsulation;

forming a first buildup dielectric layer on the encapsulation;

ablating artifacts in the first buildup dielectric layer, the ablated artifacts comprising:

at least one via hole through the first buildup dielectric layer, the at least one via hole extending through the first buildup dielectric layer in a direction perpendicular to the first substrate side; and

at least one channel in the first buildup dielectric layer, the at least one channel extending through the first buildup dielectric layer in a direction parallel to the first substrate side; and

depositing a first metal layer in the ablated artifacts to form a first electrically conductive pattern in the first buildup dielectric layer, where the first electrically conductive pattern is electrically connected to the electrically conductive via formed through the encapsulation.

8. The method of claim 7 , comprising before said forming a first buildup dielectric layer, forming an electrically conductive feature on a top surface of the encapsulation and electrically connected to the conductive via and completely covering the conductive via and the via hole, and wherein the electrically conductive pattern in the first buildup dielectric layer is electrically connected to the electrically conductive feature on the top surface of the encapsulation.

9. The method of claim 7 , wherein said covering at least the perimeter die sides and the first substrate side with an encapsulation comprises leaving the second substrate side free of the encapsulation.

10. The method of claim 7 , wherein the first buildup dielectric layer surrounds the encapsulation.

11. The method of claim 10 wherein the first buildup dielectric layer comprises sidewalls in contact with sides of the encapsulation.

12. The method of claim 7 wherein the electrically conductive via comprises a conductive material, and said forming an electrically conductive via comprises depositing the conductive material after said covering with the encapsulation.

13. The method of claim 7 , wherein said ablating artifacts in the first buildup dielectric layer comprises laser-ablating the artifacts in the first buildup dielectric layer.

14. The method of claim 7 , wherein:

the first electrically conductive pattern comprises electrically conductive vias formed within the first buildup dielectric layer and extending in a direction substantially perpendicular to a top surface of the first buildup dielectric layer; and

the first electrically conductive pattern comprises electrically conductive traces formed within the first buildup dielectric layer and extending in a direction substantially parallel to the top surface of the first buildup dielectric layer.

15. The method of claim 7 , further comprising:

forming a second buildup dielectric layer on the first buildup dielectric layer;

ablating second artifacts in the second buildup dielectric layer; and

forming a second metal layer in the ablated second artifacts to form a second electrically conductive pattern in the second buildup dielectric layer.

16. The method of claim 7 , wherein said forming the first buildup dielectric layer comprises forming the first buildup dielectric layer directly on the encapsulation.

17. A method of manufacturing a semiconductor package, the method comprising:

coupling semiconductor dies and a top side of an assembly substrate comprising substrates integrally connected together;

encapsulating the semiconductor dies and the assembly substrate to form an assembly encapsulation, wherein a bottom side of the assembly substrate is free of the assembly encapsulation;

laser-ablating via holes laterally offset from the semiconductor dies through at least the assembly encapsulation, the entirety of each of the via holes formed only by laser-ablating;

depositing conductive material within the via holes to form conductive vias;

forming a first assembly buildup dielectric layer on the assembly encapsulation;

ablating artifacts in the first assembly buildup dielectric layer;

depositing a first metal layer in the ablated artifacts to form first electrically conductive patterns in the first assembly buildup dielectric layer; and

singulating the assembly encapsulation and the first assembly buildup dielectric layer to form the semiconductor package.

18. The method of claim 17 wherein the semiconductor package comprises an encapsulation, the encapsulation being a portion of the assembly encapsulation.

19. The method of claim 17 wherein the semiconductor package comprises a substrate, the substrate being a portion of the assembly substrate.

20. The method of claim 17 wherein the semiconductor package comprises a first buildup dielectric layer, the first buildup dielectric layer being a portion of the first assembly buildup dielectric layer.