Semiconductor package and manufacturing method thereof
View Patent ↗A semiconductor package and a method of manufacturing a semiconductor package. As non-limiting examples, various aspects of this disclosure provide various semiconductor packages, and methods of making thereof, that comprise a cover layer that enhances reliability of the semiconductor packages.
1. A semiconductor package comprising:
a redistribution (RD) structure comprising an upper RD side, a lower RD side, and a lateral RD side that extends between the upper RD side and the lower RD side;
a conductive pad on the upper RD side;
a conductive post on the upper RD side, the conductive post comprising an upper post end, a lower post end, and a lateral post side that extends between the upper post end and the lower post end;
a semiconductor die on the upper RD side and electrically connected to the conductive pad;
a cover layer covering at least a portion of the semiconductor die and at least a portion of the conductive post; and
an encapsulating material that covers at least a portion of the cover layer, at least a portion of the semiconductor die, and at least a portion of the conductive post.
2. The semiconductor package of claim 1 , wherein the cover layer is a continuous layer of dielectric material.
3. The semiconductor package of claim 1 , wherein the cover layer extends up the lateral post side higher than a height of an upper side of the semiconductor die and covers an upper side of the semiconductor die.
4. The semiconductor package of claim 1 , wherein the cover layer has a generally uniform thickness.
5. The semiconductor package of claim 1 , wherein a lateral side of the cover layer, a lateral side of the RD structure, and a lateral side of the encapsulating material are coplanar.
6. The semiconductor package of claim 1 , wherein the cover layer directly contacts the conductive post and the semiconductor die.
7. The semiconductor package of claim 1 , wherein the cover layer extends laterally over the RD structure from the semiconductor die to the conductive post.
8. The semiconductor package of claim 1 , wherein the cover layer is between and keeps separate the encapsulating material and the RD structure.
9. The semiconductor package of claim 1 , wherein a continuous portion of the cover layer covers the lateral post side and extends to a lateral side of the semiconductor package.
10. The semiconductor package of claim 1 , comprising an underfill material between the semiconductor die and the upper RD side, and wherein the cover layer covers a side surface of the underfill material.
11. A semiconductor package comprising:
a redistribution (RD) structure comprising an upper RD side, a lower RD side, and a lateral RD side that extends between the upper RD side and the lower RD side;
a conductive pad on the upper RD side;
a conductive post on the upper RD side, the conductive post comprising an upper post end, a lower post end, and a lateral post side that extends between the upper post end and the lower post end;
a semiconductor die on the upper RD side and electrically connected to the conductive pad;
a cover layer covering at least a portion of the conductive post and at least a portion of the RD structure; and
an encapsulating material that covers at least a portion of the cover layer, at least a portion of the semiconductor die, and at least a portion of the conductive post.
12. The semiconductor package of claim 11 , wherein the cover layer is a continuous layer of dielectric material.
13. The semiconductor package of claim 11 , wherein the cover layer extends laterally over the RD structure from the conductive post to a second conductive post.
14. The semiconductor package of claim 11 , wherein a continuous portion of the cover layer covers the lateral post side and extends to a lateral side of the semiconductor package.
15. The semiconductor package of claim 11 , comprising an underfill material between the semiconductor die and the upper RD side, and wherein the cover layer covers a side surface of the underfill material.
16. A semiconductor package comprising:
a redistribution (RD) structure comprising an upper RD side, a lower RD side, and a lateral RD side that extends between the upper RD side and the lower RD side;
a conductive pad on the upper RD side;
a conductive post on the upper RD side, the conductive post comprising an upper post end, a lower post end, and a lateral post side that extends between the upper post end and the lower post end;
a semiconductor die on the upper RD side and electrically connected to the conductive pad;
a cover layer covering at least a portion of the semiconductor die and at least a portion of the RD structure; and
an encapsulating material that covers at least a portion of the cover layer, at least a portion of the semiconductor die, and at least a portion of the conductive post.
17. The semiconductor package of claim 16 , wherein the cover layer is a continuous layer of dielectric material.
18. The semiconductor package of claim 16 , wherein the cover layer extends laterally over the RD structure from the semiconductor die toward the conductive post.
19. The semiconductor package of claim 16 , wherein a continuous portion of the cover layer covers a lateral side of the semiconductor die and extends to a lateral side of the semiconductor package.
20. The semiconductor package of claim 16 , wherein the cover layer covers an upper side and a lateral side of the semiconductor die.