Semiconductor device and manufacturing method thereof

1. A semiconductor device comprising:

a substrate comprising:

a first substrate side, a second substrate side opposite the first substrate side, and a plurality of perimeter substrate sides extending between the first substrate side and the second substrate side;

a central pattern exposed at the first substrate side;

a dielectric layer;

a plurality of conductive vias connected to the central pattern, extending through the dielectric layer, and exposed at the second substrate side; and

an edge pattern exposed at the perimeter substrate sides and completely extending around the substrate; and

a semiconductor die coupled to the first substrate side,

wherein:

the edge pattern comprises a plurality of conductive layers exposed at the perimeter substrate sides and positioned directly laterally from the dielectric layer in a direction parallel to the first and second substrate sides;

a first conductive layer of the plurality of conductive layers comprises a plurality of perimeter sides, and extends a first distance directly laterally from the dielectric layer; and

a second conductive layer of the plurality of conductive layers comprises a plurality of perimeter sides, each of which extends a second distance directly laterally from the dielectric layer and is coplanar with a respective one of the perimeter sides of the first conductive layer, wherein the second distance is different from the first distance.

2. The semiconductor device of claim 1 , wherein:

the dielectric layer laterally surrounds the central pattern;

the dielectric layer comprises a top surface that is no lower than a top surface of the central pattern;

the semiconductor die comprises:

a first die side;

a second die side opposite the first die side, the second die side coupled to the first substrate side; and

a plurality of perimeter die sides extending between the first die side and the second die side; and

the semiconductor device further comprises a conductive interconnection structure electrically connecting the semiconductor die to the central pattern.

3. The semiconductor device of claim 2 , comprising an encapsulant on the first substrate side and covering at least the perimeter die sides, the first die side, and the second die side.

4. The semiconductor device of claim 1 , wherein a conductive via of the plurality of conductive vias extends directly from the central pattern to the second substrate side and comprises a surface that is coplanar with the second substrate side.

5. The semiconductor device of claim 1 , wherein one of the first conductive layer and the second conductive layer is plated directly on the other of the first conductive layer and the second conductive layer.

6. The semiconductor device of claim 1 , wherein the edge pattern is laterally wider at the first substrate side than at the second substrate side.

7. The semiconductor device of claim 2 , wherein the second conductive layer, in a direction perpendicular to the first substrate side, is thicker than the first conductive layer.

8. A semiconductor device comprising:

a substrate comprising:

a first substrate side, a second substrate side opposite the first substrate side, and a plurality of perimeter substrate sides extending between the first substrate side and the second substrate side;

a central pattern exposed at the first substrate side;

a dielectric layer;

a plurality of conductive vias connected to the central pattern, extending through the dielectric layer, and exposed at the second substrate side; and

an edge pattern exposed at the perimeter substrate sides and completely extending around the substrate; and

a semiconductor die coupled to the first substrate side,

wherein the edge pattern comprises a plurality of conductive layers exposed at the perimeter substrate sides and positioned directly laterally from the dielectric layer in a direction parallel to the first and second substrate sides; and

wherein the plurality of conductive layers of the edge pattern comprise:

a first conductive layer at the perimeter substrate sides and having a first lateral width directly laterally from the dielectric layer; and

a second conductive layer at the perimeter substrate sides and having a second lateral width directly laterally from the dielectric layer, wherein the second lateral width is less than the first lateral width.

9. The semiconductor device of claim 8 , wherein:

respective outer perimeter surfaces of the first and second conductive layers are coplanar at the perimeter substrate sides; and

respective inner surfaces of the first and second conductive layers meet at a step-shaped interface.

10. The semiconductor device of claim 8 , wherein the first and the second conductive layer metal are the same type of metal.

11. The semiconductor device of claim 8 , wherein:

the first conductive layer extends directly laterally from the dielectric layer a first distance;

the second conductive layer extends directly laterally from the dielectric layer a second distance different from the first distance; and

respective outer perimeter surfaces of the first and second conductive layer are coplanar.

12. The semiconductor device of claim 8 , wherein an outer perimeter surface of each of the first and second conductive layers comprises a sawn surface.

13. A semiconductor device comprising:

a substrate comprising:

a first substrate side, a second substrate side opposite the first substrate side, and a plurality of perimeter substrate sides extending between the first substrate side and the second substrate side;

a central pattern exposed at the first substrate side;

a dielectric layer;

a plurality of conductive vias connected to the central pattern, extending through the dielectric layer, and exposed at the second substrate side; and

an edge pattern exposed at the perimeter substrate sides and completely extending around the substrate; and

a semiconductor die coupled to the first substrate side,

wherein the edge pattern comprises a plurality of conductive layers exposed at the perimeter substrate sides and positioned directly laterally from the dielectric layer in a direction parallel to the first and second substrate sides;

wherein the plurality of conductive layers comprise:

a first conductive layer exposed at the perimeter substrate sides and at the first substrate side; and

a second conductive layer exposed at the perimeter substrate sides and at the second substrate side; and

wherein interior surfaces of the first and second conductive layers meet at an interface that comprises a step, and the step is entirely covered by the dielectric layer.

14. The semiconductor device of claim 13 , wherein the edge pattern continuously extends around the substrate.

15. The semiconductor device of claim 13 , wherein the dielectric layer comprises only a single continuous layer of molding material contacting and covering at least one lateral surface of each of: the central pattern, the plurality of conductive vias, and the plurality of conductive layers of the edge pattern.

16. The semiconductor device of claim 13 , wherein:

the first conductive layer comprises a sawn surface; and

the second conductive layer comprises a sawn surface that is coplanar with the sawn surface of the first conductive layer.

17. The semiconductor device of claim 16 , wherein:

the first conductive layer extends directly laterally from the dielectric layer; and

the second conductive layer extends directly laterally from the dielectric layer.

18. The semiconductor device of claim 16 , wherein the first and second conductive layers extend directly laterally from the dielectric layer different respective distances.

19. The semiconductor device of claim 16 , further comprising:

an encapsulant on the first substrate side and covering at least perimeter sides of the semiconductor die,

wherein the encapsulant comprises a plurality of perimeter sides, each of which is coplanar with a respective perimeter side of the first conductive layer and with a respective perimeter side of the second conductive layer.