Extended landing pad substrate package structure and method
View Patent ↗An extended landing pad substrate package includes a dielectric layer having an upper surface and an opposite lower surface. A lower circuit pattern is embedded in the lower surface of the dielectric layer. The lower circuit pattern includes traces having a first thickness and extended landing pads having a second thickness greater than the first thickness. Blind via apertures are formed through an upper circuit pattern embedded into the upper surface of the dielectric layer, through the dielectric layer and to the extended landing pads. The length of the blind via apertures is minimized due to the increase second thickness of the extended landing pads as compared to the first thickness of traces. Accordingly, the width of the blind via apertures at the upper surface of the dielectric layer is minimized.
1. A method of forming an extended landing pad substrate package, the method comprising:
plating a primary conductor layer, the primary conductor layer comprising:
a trace having a first thickness; and
an extended landing pad foundation portion having the first thickness;
selectively plating an extension conductor layer on the extended landing pad foundation portion but not on the trace, the extension conductor layer comprising:
an extended landing pad extension portion on the extended landing pad foundation portion, the extended landing pad extension portion and the extended landing pad foundation portion forming an extended landing pad having a second thickness greater than the first thickness;
laminating a first circuit pattern comprising the trace and the extended landing pad into a dielectric layer; and
forming a blind via aperture extending through the dielectric layer and to the extended landing pad.
2. The method of claim 1 comprising forming a seed layer on a carrier, and wherein said plating a primary conductor layer comprises:
applying a primary resist to the seed layer;
patterning the primary resist to define a circuit pattern artifact in the primary resist; and
at least partially filling the circuit pattern artifact with the primary conductor layer.
3. The method of claim 1 wherein said laminating comprises embedding the first circuit pattern into a first surface of the dielectric layer, the method comprising laminating a second circuit pattern into a second surface of the dielectric layer, the blind via aperture extending from the second surface of the dielectric layer to the extended landing pad.
4. The method of claim 3 comprising forming a blind via in the blind via aperture, the blind via electrically connecting the first circuit pattern and the second circuit pattern.
5. A method of forming an extended landing pad substrate package, the method comprising:
forming a seed layer on a carrier;
plating a primary conductor layer, the primary conductor layer comprising:
a trace having a first thickness; and
an extended landing pad foundation portion having the first thickness;
selectively plating an extended landing pad extension portion on the extended landing pad foundation portion, the extended landing pad extension portion and the extended landing pad foundation portion forming an extended landing pad having a second thickness greater than the first thickness;
laminating a first circuit pattern comprising the trace and the extended landing pad into a dielectric layer; and
forming a blind via aperture extending through the dielectric layer and to the extended landing pad,
wherein said plating a primary conductor layer comprises:
applying a primary resist to the seed layer;
patterning the primary resist to define a circuit pattern artifact in the primary resist; and
at least partially filling the circuit pattern artifact with the primary conductor layer, and
wherein said selectively plating comprises:
applying a secondary resist to the primary resist and to the primary conductor layer;
patterning the secondary resist to expose at least a portion of the extended landing pad foundation portion; and
plating a secondary conductor layer on the exposed extended landing pad foundation portion, wherein the secondary conductor layer forms the extended landing pad extension portion.
6. The method of claim 5 comprising stripping the primary resist and the secondary resist.
7. A method of forming an extended landing pad substrate package, the method comprising:
applying a primary mask;
patterning the primary mask to define a circuit pattern artifact;
plating a primary conductor layer in the circuit pattern artifact, the primary conductor layer comprising:
a trace having a first thickness; and
an extended landing pad foundation having the first thickness;
applying a secondary mask to the primary mask and to the primary conductor layer;
patterning the secondary mask to define an extended landing pad overlay pattern artifact that exposes at least a portion of the extended landing pad foundation;
selectively plating an extended landing pad extension on the extended landing pad foundation through the extended landing pad overlay pattern artifact, where an extended landing pad comprising the extended landing pad foundation and the extended landing pad extension has a second thickness greater than the first thickness;
removing the primary and secondary masks;
embedding a first circuit pattern comprising the trace and the extended landing pad in a dielectric layer; and
forming a blind via aperture extending through the dielectric layer and to the extended landing pad.
8. The method of claim 7 , wherein the circuit pattern artifact comprises an extended landing pad pattern artifact in which the extended landing pad foundation is plated, and the extended landing pad overlay pattern artifact has a different width than the extended landing pad pattern artifact.
9. The method of claim 8 , wherein the extended landing pad overlay pattern artifact has a greater width than the extended landing pad pattern artifact.
10. The method of claim 7 , wherein the extended landing pad foundation comprises a vertical side, and the extended landing pad extension comprises a vertical side.
11. The method of claim 10 , wherein the respective vertical sides of the extended landing pad foundation and the extended landing pad extension are aligned.
12. The method of claim 7 , wherein said forming a blind via aperture comprises forming the blind via aperture with sloped sides.
13. The method of claim 7 , comprising coupling a conductive ball to the extended landing pad foundation.
14. The method of claim 13 , comprising directly attaching the conductive ball to the extended landing pad foundation.
15. The method of claim 7 , wherein said laminating comprises pressing the first circuit pattern into the dielectric layer.
16. A method of forming an extended landing pad substrate package, the method comprising:
applying a primary mask;
patterning the primary mask to define a circuit pattern artifact;
plating a primary conductor layer in the circuit pattern artifact, the primary conductor layer comprising:
a trace having a first thickness; and
an extended landing pad foundation having the first thickness;
applying a secondary mask to the primary mask and to the primary conductor layer;
patterning the secondary mask to define an extended landing pad overlay pattern artifact that exposes at least a portion of the extended landing pad foundation;
selectively plating an extended landing pad extension on the extended landing pad foundation through the extended landing pad overlay pattern artifact, where an extended landing pad comprising the extended landing pad foundation and the extended landing pad extension has a second thickness greater than the first thickness;
removing the primary and secondary masks;
embedding a first circuit pattern comprising the trace and the extended landing pad in a first surface of a dielectric layer;
forming a blind via aperture extending through the dielectric layer and to the extended landing pad; and
embedding a second circuit pattern having a third thickness in a second surface of the dielectric layer, where the second thickness of the extended landing pad is greater than the third thickness of the second circuit pattern.
17. The method of claim 16 , wherein the second thickness of the extended landing pad is at least two times greater than the third thickness of the second circuit pattern.
18. The method of claim 17 , wherein the second thickness of the extended landing pad is at most three times greater than the third thickness of the second circuit pattern.
19. The method of claim 16 , wherein said embedding a first circuit pattern comprises pressing the first circuit pattern into the dielectric layer.
20. The method of claim 19 , wherein said embedding a second circuit pattern comprises pressing the second circuit pattern into the dielectric layer simultaneously with said pressing the first circuit pattern into the dielectric layer.