Semiconductor device and manufacturing method thereof
View Patent ↗A semiconductor device includes a low-density substrate, a high-density patch positioned inside a cavity in the low-density substrate, a first semiconductor die, and a second semiconductor die. The first semiconductor dies includes high-density bumps and low-density bumps. The second semiconductor die includes high-density bumps and low-density bumps. The high-density bumps of the first semiconductor die and the high-density bumps of the second semiconductor die are electrically connected to the high-density patch. The low-density bumps of the first semiconductor die and the low-density bumps of the second semiconductor die are electrically connected to the low-density substrate.
1. A semiconductor device comprising:
a low-density substrate;
a high-density patch positioned inside a cavity in the low-density substrate, the high-density patch comprising a base plate and a high-density redistribution structure, wherein the high-density redistribution structure comprises one or more high-density circuit traces on the base plate;
a first semiconductor die including high-density bumps and low-density bumps; and
a second semiconductor die including high-density bumps and low-density bumps,
wherein the high-density bumps of the first semiconductor die and the high-density bumps of the second semiconductor die are electrically connected to the one or more high-density circuit traces of the high-density patch, and the low-density bumps of the first semiconductor die and the low-density bumps of the second semiconductor die are electrically connected to the low-density substrate.
2. The semiconductor device of claim 1 , wherein:
the high-density redistribution structure further comprises one or more dielectric layers; and
the low-density substrate includes a low-density redistribution structure having one or more low-density circuit traces and one or more dielectric layers.
3. The semiconductor device of claim 1 , wherein the high-density patch further comprises high-density interconnects interposed between the one or more high-density circuit traces and the high-density bumps.
4. The semiconductor device of claim 3 , further comprising an underfill that surrounds the high-density interconnects.
5. The semiconductor device of claim 1 , wherein the low-density substrate comprises:
a first dielectric layer;
low-density pillars through the first dielectric layer; and
a low-density redistribution structure under the first dielectric layer and the low-density pillars;
wherein the low-density pillars are interposed between the low-density bumps and one or more low-density circuit traces of the low-density redistribution structure.
6. The semiconductor device of claim 3 , wherein the low-density substrate comprises:
a first dielectric layer;
low-density pillars through the first dielectric layer; and
a low-density redistribution structure under the first dielectric layer and the low-density pillars;
wherein the low-density pillars are interposed between the low-density bumps and one or more low-density circuit traces of the low-density redistribution structure; and
wherein top surfaces of the high-density interconnects and top surfaces of the low-density pillars are coplanar.
7. The semiconductor device of claim 5 , wherein:
the low-density redistribution structure comprises a second dielectric layer;
the first and second dielectric layers comprise resins; and
the first dielectric layer comprises a larger amount of inorganic fillers than the second dielectric layer.
8. The semiconductor device of claim 5 , wherein:
the low-density redistribution structure comprises a second dielectric layer;
the first dielectric layer comprises an epoxy molding compound; and
the second dielectric layer comprises a resin that is softer than the epoxy molding compound.
9. The semiconductor device of claim 5 , wherein a bottom surface of the high-density patch contacts a top surface of the low-density redistribution structure.
10. The semiconductor device of claim 1 , wherein side surfaces of the high-density patch contact side surfaces of the cavity.
11. The semiconductor device of claim 1 , wherein the high-density bumps of the first and second semiconductor dies and the low-density bumps of the first and second semiconductor dies are equal in height.
12. A manufacturing method of a semiconductor device comprising:
forming high-density interconnects and low-density pillars on a first carrier;
electrically connecting a high-density patch to the high-density interconnects;
forming a low-density substrate over the high-density patch and the low-density pillars such that a first dielectric layer of the low-density substrate encompasses the low-density pillars;
removing the first carrier to expose the high-density patch and the low-density pillars; and
electrically connecting a first semiconductor die and a second semiconductor die to the high-density patch and the low-density pillars.
13. The manufacturing method of claim 12 , wherein said forming the low-density substrate comprises forming a low-density redistribution structure over the first dielectric layer such that one or more low-density circuit patterns of the low-density redistribution structure are electrically connected to the low-density pillars.
14. The manufacturing method of claim 13 , wherein said forming the low-density redistribution structure comprises forming one or more second dielectric layers such that a second dielectric layer of the one or more second dielectric layers lies between an overlying low-density circuit pattern and an underlying low-density circuit pattern of the one or more low-density circuit patterns.
15. The manufacturing method of claim 12 , further comprising:
forming conductive bumps on the low-density substrate;
adhering a second carrier to the low-density substrate by applying an adhesive to the conductive bumps; and
removing the first carrier after said adhering.
16. The manufacturing method of claim 12 , wherein said electrically connecting the first semiconductor die and the second semiconductor die comprises electrically connecting the first semiconductor die to the second semiconductor die by electrically connecting high-density bumps of the first semiconductor die and high-density bumps of the second semiconductor die to the high-density patch.
17. The manufacturing method of claim 16 , wherein said electrically connecting the first semiconductor die and the second semiconductor die further comprises electrically connecting low-density bumps of the first semiconductor die and low-density bumps of the second semiconductor die to the low-density substrate.
18. The semiconductor device of claim 1 , wherein the base plate comprises silicon.
19. The semiconductor device of claim 5 , wherein the cavity extends through the first dielectric layer and exposes a surface of the low-density substrate.
20. The semiconductor device of claim 1 , wherein each low-density bump of the first semiconductor die includes a conductive pillar having a solder cap.