IP Library Granted Patent US 8,937,381
Granted Patent B1
US 8,937,381 · App. 12/630,586 · Granted Jan 20, 2015

Thin stackable package and method

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,937,381
App. No.
12/630,586
Granted
Jan 20, 2015
Kind
B1
Abstract

A fan out buildup substrate stackable package includes an electronic component having an active surface having bond pads. A package body encloses the electronic component. A first die side buildup dielectric layer is applied to the active surface of the electronic component and to a first surface of the package body. A first die side circuit pattern is formed on the first die side buildup dielectric layer and electrically connected to the bond pads. Through vias extend through the package body and the first die side buildup dielectric layer, the through vias being electrically connected to the first die side circuit pattern. The fan out buildup substrate stackable package is extremely thin and provides a high density interconnect on both sides of the package allowing additional devices to be stacked thereon.

Claims (88)

1. A fan out buildup substrate stackable package comprising:

an electronic component comprising:

an active surface comprising bond pads;

sides;

an inactive surface; and

through electronic component vias extending through the electronic component between the active surface and the inactive surface of the electronic component, wherein ends of the through electronic component vias at the active surface define active surface through via terminals;

a package body enclosing the electronic component and directly contacting the sides;

a first die side buildup dielectric layer applied to the active surface of the electronic component and a first surface of the package body, a second surface of the package body being coplanar with the inactive surface of the electronic component;

a first die side circuit pattern in contact with the first die side buildup dielectric layer and electrically connected to the bond pads; and

through vias extending through the package body and the first die side buildup dielectric layer, the through vias being electrically connected to the first die side circuit pattern.

2. The fan out buildup substrate stackable package of claim 1 wherein the first die side circuit pattern comprises:

bond pad vias extending entirely through the first die side buildup dielectric layer and being electrically connected to the bond pads;

lands electrically connected to the through vias; and

traces electrically connecting the bond pad vias to the lands.

3. The fan out buildup substrate stackable package of claim 1 further comprising:

a second die side buildup dielectric layer applied to the first die side buildup dielectric layer and to the first die side circuit pattern; and

a second die side circuit pattern in contact with the second die side buildup dielectric layer and electrically connected to the first die side circuit pattern, the second die side circuit pattern comprising lands.

4. The fan out buildup substrate stackable package of claim 1 further comprising:

a first mold side buildup dielectric layer applied to the second surface of the package body; and

a first mold side circuit pattern in contact with the first mold side buildup dielectric layer and electrically connected to the through vias.

5. The fan out buildup substrate stackable package of claim 4 wherein the first mold side circuit pattern comprises: lands electrically connected to the through vias; and traces electrically connected to the lands.

6. The fan out buildup substrate stackable package of claim 4 further comprising:

a second mold side buildup dielectric layer applied to the first mold side buildup dielectric layer and to the first mold side circuit pattern; and

a second mold side circuit pattern in contact with the second mold side buildup dielectric layer and electrically connected to the first mold side circuit pattern, the second mold side circuit pattern comprising lands.

7. The fan out buildup substrate stackable package of claim 1 wherein the through vias comprise:

sidewall layers; and

fillings.

8. The fan out buildup substrate stackable package of claim 1 wherein first ends of the through vias define mold side lands.

9. The fan out buildup substrate stackable package of claim 8 further comprising interconnection balls on the mold side lands.

10. A fan out buildup substrate stackable package comprising:

an electronic component comprising:

an active surface comprising bond pads;

sides;

an inactive surface; and

through electronic component vias extending through the electronic component between the active surface and the inactive surface of the electronic component, wherein ends of the through electronic component vias at the active surface define active surface through via terminals;

a package body enclosing the electronic component and directly contacting the sides and the inactive surface;

a first die side buildup dielectric layer applied to the active surface of the electronic component and a first surface of the package body, a second surface of the package body being above and spaced apart from the inactive surface of the electronic component; a first die side circuit pattern in contact with the first die side buildup dielectric layer and electrically connected to the bond pads; and

through vias extending through the package body and the first die side buildup dielectric layer, the through vias being electrically connected to the first die side circuit pattern.

11. A fan out buildup substrate stackable package comprising:

an electronic component comprising:

an active surface comprising bond pads;

through electronic component vias extending through the electronic component between the active surface and the inactive surface of the electronic component, wherein ends of the through electronic component vias at the active surface define active surface through via terminals; and

inactive surface through via terminals defined by ends of the through electronic component vias at the inactive surface of the electronic component;

a package body enclosing the electronic component;

a first die side buildup dielectric layer applied to the active surface of the electronic component and a first surface of the package body;

a first die side circuit pattern in contact with the first die side buildup dielectric layer and electrically connected to the bond pads and the active surface through via terminals; and

through vias extending through the package body and the first die side buildup dielectric layer, the through vias being electrically connected to the first die side circuit pattern.

12. The fan out buildup substrate stackable package of claim 11 further comprising:

a first mold side buildup dielectric layer applied to a second surface of the package body; and

a first mold side circuit pattern in contact with the first mold side buildup dielectric layer and electrically connected to the inactive surface through via terminals.

13. An assembly comprising:

a fan out buildup substrate stackable package comprising:

an electronic component comprising:

an active surface comprising bond pads;

sides;

an inactive surface; and

through electronic component vias extending through the electronic component between the active surface and the inactive surface of the electronic component, wherein ends of the through electronic component vias at the active surface define active surface through via terminals;

a package body enclosing the electronic component and directly contacting the sides;

a first die side buildup dielectric layer applied to the active surface of the electronic component and a first surface of the package body, a second surface of the package body being coplanar with the inactive surface of the electronic component;

a first die side circuit pattern in contact with the first die side buildup dielectric layer and electrically connected to the bond pads; and

through vias extending through the package body and the first die side buildup dielectric layer, the through vias being electrically connected to the first die side circuit pattern; and

a stacked device stacked on the fan out buildup substrate stackable package.

14. The assembly of claim 13 wherein the stacked device comprises a stacked electronic component.

15. The assembly of claim 13 wherein the stacked device comprises a stacked electronic component package.

16. The assembly of claim 13 wherein the stacked device comprises:

a second fan out buildup substrate stackable package comprising:

an electronic component comprising an active surface comprising bond pads;

a package body enclosing the electronic component of the second fan out buildup substrate stackable package;

a first die side buildup dielectric layer applied to the active surface of the electronic component and a first surface of the package body of the second fan out buildup substrate stackable package;

a first die side circuit pattern in contact with the first die side buildup dielectric layer and electrically connected to the bond pads of the second fan out buildup substrate stackable package; and

through vias extending through the package body and the first die side buildup dielectric layer of the second fan out buildup substrate stackable package, the through vias of the second fan out buildup substrate stackable package being electrically connected to the first die side circuit pattern of the second fan out buildup substrate stackable package.

17. A fan out buildup substrate stackable package comprising:

an electronic component comprising:

an active surface comprising bond pads;

sides;

an inactive surface; and

through electronic component vias extending through the electronic component between the active surface and the inactive surface of the electronic component, wherein ends of the through electronic component vias at the active surface define active surface through via terminals;

a package body enclosing the electronic component and directly contacting the sides; a first die side buildup dielectric layer applied to the active surface of the electronic component and a first surface of the package body, a second surface of the package body being coplanar with the inactive surface of the electronic component;

a first die side circuit pattern in contact with the first die side buildup dielectric layer, the first die side circuit pattern comprising:

bond pad vias extending entirely through the first die side buildup dielectric layer and being electrically connected to the bond pads;

lands; and

traces electrically connecting the bond pad vias to the lands; and

through vias extending through the package body and the first die side buildup dielectric layer, the through vias being electrically connected to the lands.

18. The fan out buildup substrate stackable package of claim 17 further comprising:

a first mold side buildup dielectric layer applied to the second surface of the package body; and

a first mold side circuit pattern in contact with the first mold side buildup dielectric layer, the first mold side circuit pattern comprising:

lands electrically connected to the through vias; and

traces electrically connected to the lands.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 12, 2020
From: AMKOR TECHNOLOGY, INC.
To: AMKOR TECHNOLOGY SINGAPORE HOLDING PTE.LTD.
Reel/Frame 054046/0673 →
SECURITY INTEREST Recorded Aug 1, 2018
From: AMKOR TECHNOLOGY, INC.
To: BANK OF AMERICA, N.A., AS AGENT
Reel/Frame 046683/0139 →
PATENT SECURITY AGREEMENT Recorded May 7, 2015
From: AMKOR TECHNOLOGY, INC.
To: BANK OF AMERICA, N.A.
Reel/Frame 035613/0592 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 3, 2009
From: DUNLAP, BRETT ARNOLD; COPIA, ALEXANDER WILLIAM
To: AMKOR TECHNOLOGY, INC.
Reel/Frame 023602/0072 →