Flip chip bump structure and fabrication method
View Patent ↗A method includes forming a patterned buildup layer on a first surface of a dielectric layer, the patterned buildup layer including a patterned buildup layer opening exposing a trace coupled to the dielectric layer. A conductor layer is flash plated on the patterned buildup layer and within the patterned buildup layer opening. The patterned buildup layer opening is filled with a blanket conductive filler layer. The blanket conductive filler layer and the conductor layer are planarized to form a flip chip bump.
1. A flip chip bump structure comprising:
a dielectric layer;
a trace coupled to the dielectric layer;
a patterned buildup layer on a first surface of the dielectric layer, the patterned buildup layer comprising a patterned buildup layer opening exposing a portion of the trace, the portion of the trace exposed within the patterned buildup layer opening having a uniform width, a diameter of the patterned buildup layer opening being greater than the uniform width of the portion of the trace exposed within the patterned buildup layer opening;
a portion of a conductor layer remaining in the patterned buildup layer opening and directly contacting the portion of the trace exposed within the patterned buildup layer opening and
a flip chip bump in the patterned buildup layer opening, the flip chip bump extending horizontally outward from the patterned buildup layer opening over the patterned buildup layer.
2. The flip chip bump structure of claim 1 wherein the flip chip bump comprises copper.
3. The flip chip bump structure of claim 1 wherein the portion of the conductor layer further extends horizontally outward from the patterned buildup layer opening over the patterned buildup layer.
4. The flip chip bump structure of claim 3 wherein the flip chip bump is formed directly on the portion of the conductor layer.
5. The flip chip bump structure of claim 3 wherein the flip chip bump is coupled to the trace by the portion of the conductor layer.
6. The flip chip bump structure of claim 1 further comprising:
a lower circuit pattern coupled to a second surface of the dielectric layer, the lower circuit pattern comprising a land; and
an interconnection ball directly on the land.
7. The flip chip bump structure of claim 1 further comprising:
an electronic component comprising an active surface comprising a bond pad, the bond pad being physically and electrically coupled to the flip chip bump.
8. The flip chip bump structure of claim 1 further comprising an upper circuit pattern comprising the trace and a second trace, the patterned buildup layer covering and electrically isolating the second trace.
9. The flip chip bump structure of claim 1 wherein the trace is embedded in the dielectric layer.
10. The flip chip bump structure of claim 1 wherein a diameter of the flip chip bump is greater than the uniform width of the portion of the trace exposed within the patterned buildup layer opening.
11. The flip chip bump structure of claim 1 wherein the patterned buildup layer opening is a cylindrical opening.
12. The flip chip bump structure of claim 1 , wherein the flip chip bump comprises metal that is plated on the conductor layer.
13. The flip chip bump structure of claim 1 , wherein the conductor layer is a plated seed layer comprising copper.
14. The flip chip bump structure of claim 13 , wherein the flip chip bump comprises copper plated on the conductor layer.
15. The flip chip bump structure of claim 1 , wherein the flip chip bump is planarized.
16. The flip chip bump structure of claim 1 , wherein the trace is embedded in the dielectric layer.
17. The flip chip bump structure of claim 1 , wherein the pattered buildup layer opening has a circular cross-section.
18. A flip chip bump structure comprising:
a patterned buildup layer formed on a first surface of a dielectric layer, the patterned buildup layer comprising a patterned buildup layer opening exposing a trace and portions of the first surface of the dielectric layer;
a conductor layer plated on the patterned buildup layer and within the patterned buildup layer opening;
a patterned resist formed on the conductor layer, the patterned resist comprising a flip chip bump opening having a diameter greater than a diameter of the patterned buildup layer opening; and
a flip chip bump filling the flip chip bump opening and the patterned buildup layer opening.
19. The flip chip bump structure of claim 18 wherein the flip chip bump opening and the patterned buildup layer opening form a variable diameter opening.
20. The flip chip bump structure of claim 18 wherein the flip chip bump comprises copper.