Stacked inverted flip chip package and fabrication method

1. A stacked inverted flip chip package comprising:

a substrate comprising:

a secondary electronic component opening;

first traces;

a dielectric layer, the first traces being embedded within a first surface of the dielectric layer; and

a first solder mask coupled to the first surface of the dielectric layer, the secondary electronic component opening being formed within the first solder mask only, a central portion of the first surface of the dielectric layer being exposed through the secondary electronic component opening;

a primary electronic component structure comprising:

substrate terminals; and

secondary electronic component terminals;

primary flip chip bumps electrically and physically coupling the substrate terminals to the first traces;

a secondary electronic component comprising bond pads, the secondary electronic component extending into the secondary electronic component opening, the first traces extending within a plane along the first surface of the dielectric layer laterally from outside the central portion to within the central portion directly below the secondary electronic component; and

secondary flip chip bumps electrically and physically coupling the bond pads to the secondary electronic component terminals, wherein a distance between the primary electronic component structure and the secondary electronic component is less than a distance between the primary electronic component structure and the substrate.

2. A stacked inverted flip chip package comprising:

a substrate comprising:

a secondary electronic component opening; and

first traces;

a primary electronic component structure comprising:

substrate terminals; and

secondary electronic component terminals;

primary flip chip bumps electrically and physically coupling the substrate terminals to the first traces;

a secondary electronic component comprising bond pads, the secondary electronic component extending into the secondary electronic component opening;

secondary flip chip bumps electrically and physically coupling the bond pads to the secondary electronic component terminals, wherein a distance between the primary electronic component structure and the secondary electronic component is less than a distance between the primary electronic component structure and the substrate;

a nonconductive paste filling a space between the secondary electronic component and the substrate;

a capillary underfill material filling a space between a first surface of the primary electronic component structure and the substrate, between the secondary electronic component and the first surface of the primary electronic component structure, and enclosing the nonconductive paste, a second surface and sides of the primary electronic component structure being completely exposed from the capillary underfill material, wherein the capillary underfill material contacts the entire first surface of the primary electronic component structure; and

a molding compound enclosing the second surface and the entire sides of the primary electronic component structure and the capillary underfill material,

wherein the substrate further comprises:

a dielectric layer, the first traces being coupled to a first surface of the dielectric layer; and

a first solder mask coupled to the first surface of the dielectric layer, the secondary electronic component opening being formed within the first solder mask, a central portion of the first surface of the dielectric layer being exposed through the secondary electronic component opening.

3. The stacked inverted flip chip package of claim 2 wherein the secondary electronic component opening extends entirely through the first solder mask and partially into the dielectric layer.

4. The stacked inverted flip chip package of claim 2 wherein the central portion of the first surface of the dielectric layer has an absence of the first traces.

5. The stacked inverted flip chip package of claim 2 wherein the substrate further comprises:

second traces on a second surface of the dielectric layer; and

vias electrically coupling the second traces to the first traces.

6. The stacked inverted flip chip package of claim 1 wherein the primary flip chip bumps comprise solder bumps.

7. The stacked inverted flip chip package of claim 1 wherein the primary flip chip bumps comprise copper pillars.

8. The stacked inverted flip chip package of claim 1 wherein the secondary flip chip bumps comprise solder bumps.

9. The stacked inverted flip chip package of claim 1 wherein the secondary flip chip bumps comprise copper pillars.

10. The stacked inverted flip chip package of claim 1 further comprising a nonconductive paste filling a space between the secondary electronic component and the substrate.

11. The stacked inverted flip chip package of claim 1 further comprising an underfill material filling a space between the primary electronic component structure and the secondary electronic component.

12. The stacked inverted flip chip package of claim 1 wherein the primary electronic component structure further comprises:

a primary electronic component comprising a first surface comprising bond pads thereon;

a patterned passivation layer on the first surface of the primary electronic component, the patterned passivation layer exposing the bond pads;

primary electronic component redistribution layer (RDL) traces on the patterned passivation layer, the primary electronic component RDL traces being electrically connected to the bond pads;

secondary electronic component RDL traces on the patterned passivation layer;

a patterned dielectric layer formed on the patterned passivation layer, the primary electronic component RDL traces, and the secondary electronic component RDL traces, wherein the patterned dielectric layer exposes the substrate terminals of the primary electronic component RDL traces and the secondary electronic component RDL traces and the secondary electronic component terminals of the secondary electronic component RDL traces, wherein the secondary flip chip bumps are smaller than the primary flip chip bumps.

13. The stacked inverted flip chip package of claim 12 wherein the primary electronic component structure further comprises a patterned passivation buildup layer on the patterned passivation layer.