Semiconductor device and manufacturing method thereof
View Patent ↗A semiconductor package and a manufacturing method thereof, which can reduce the size of the semiconductor package and improve product reliability. In a non-limiting example embodiment, the method may comprise forming an interposer on a wafer, forming at least one reinforcement member on the interposer, coupling and electrically connecting at least one semiconductor die to the interposer to the interposer, filling a region between the semiconductor die and the interposer with an underfill, and encapsulating the reinforcement member, the semiconductor die and the underfill on the interposer using an encapsulant.
1. A method for fabricating a semiconductor package, the method comprising:
forming a substrate on a wafer;
forming at least one reinforcement member on a portion of a perimeter of the substrate, wherein the at least one reinforcement member comprises a conductive material;
coupling and electrically connecting at least one semiconductor die to the substrate; and
encapsulating the at least one reinforcement member and the semiconductor die on the substrate with an encapsulant.
2. The method according to claim 1 , wherein forming the at least one reinforcement member comprises forming a plurality of discrete reinforcement members.
3. The method according to claim 1 , wherein forming the at least one reinforcement member comprises forming a closed perimeter wall along the perimeter of the substrate.
4. The method according to claim 1 , comprising underfilling a space between the semiconductor die and the substrate.
5. The method according to claim 4 , wherein the underfilling comprises underfilling prior to the encapsulating.
6. The method according to claim 5 , wherein the underfilling results in an underfill that extends to the at least one reinforcement member.
7. The method according to claim 5 , wherein the underfilling results in an underfill that does not extend to the at least one reinforcement member.
8. The method according to claim 1 , comprising, after said encapsulating:
removing the wafer from the substrate and forming conductive bumps on a surface of the substrate that was covered by the wafer; and
sawing the substrate to form a discrete semiconductor package.
9. The method according to claim 1 , comprising forming a shielding layer that surrounds the encapsulant and is electrically connected to the at least one reinforcement member.
10. The method according to claim 1 , comprising forming through mold vias (TMVs) from a top surface of the encapsulant to the top surface of the substrate.
11. A semiconductor package comprising:
a substrate;
at least one reinforcement member on the substrate, wherein each of the at least one reinforcement member comprises a conductive material;
at least one semiconductor die coupled to the substrate and electrically connected to a first surface of the substrate; and
an encapsulant encapsulating the at least one reinforcement member and the at least one semiconductor die on the substrate.
12. The semiconductor package according to claim 11 , wherein the at least one reinforcement member comprises a plurality of discrete reinforcement members.
13. The semiconductor package according to claim 11 , wherein the at least one reinforcement member comprises a closed perimeter wall along a perimeter of the substrate.
14. The semiconductor package according to claim 11 , wherein, under the encapsulant, there is an underfill, between the semiconductor die and the substrate, that contacts a vertical surface of the at least one reinforcement member.
15. The semiconductor package according to claim 11 , wherein, under the encapsulant, there is an underfill, between the semiconductor die and the substrate, that does not contact any of the at least one reinforcement member.
16. The semiconductor package according to claim 11 , wherein the substrate is a printed circuit board.
17. The semiconductor package according to claim 11 , comprising conductive bumps, on a second surface of the substrate opposite the first surface, electrically connected to the substrate.
18. The semiconductor package according to claim 11 , comprising a shielding layer that surrounds the encapsulant and is electrically connected to the at least one reinforcement member.
19. The semiconductor package according to claim 11 , comprising through mold vias (TMVs) passing through a region ranging from a top surface of the encapsulant to the top surface of the substrate, wherein each of the TMVs are positioned between the semiconductor die and one of the at least one reinforcement member.
20. A semiconductor package comprising:
a substrate on a wafer;
at least one reinforcement member on the substrate, wherein the at least one reinforcement member comprises a conductive material;
at least one semiconductor die coupled and electrically connected to the substrate; and
an encapsulant that covers the at least one reinforcement member and the at least one semiconductor die,
wherein:
the substrate comprises vertical surfaces at ends of the substrate,
each of the at least one reinforcement member has an internal vertical surface that faces the at least one semiconductor die and an external vertical surface opposite the internal vertical surface,
the encapsulant has vertical surfaces at ends of the encapsulant, and
the external vertical surface of the each of the at least one reinforcement member, a corresponding one of the vertical surfaces of the substrate, and a corresponding one of the vertical surfaces of the encapsulant are substantially coplanar with each other.