Semiconductor package and fabricating method thereof
A semiconductor device structure, for example a 3D structure, and a method for fabricating a semiconductor device. As non-limiting examples, various aspects of this disclosure provide various semiconductor package structures, and methods for manufacturing thereof, that comprise interposer, interlayer, and/or heat dissipater configurations that provide for low cost, increased manufacturability, and high reliability.
1. A semiconductor package comprising:
a substrate comprising a top substrate side, a bottom substrate side, a plurality of lateral substrate sides between the top and bottom substrate sides, and a top substrate circuit pattern on the top substrate side;
a semiconductor die mounted on the top substrate side, the semiconductor die comprising a top die side, a bottom die side facing the top substrate side, and a plurality of lateral die sides;
an encapsulating material comprising a top encapsulant side and a bottom encapsulant side facing the top substrate side, where the encapsulating material encapsulates at least the lateral die sides and at least a portion of the top substrate side;
an interposer comprising:
a top interposer side,
a bottom interposer side facing the top encapsulant side,
a plurality of lateral interposer sides, and
a bottom interposer circuit pattern on the bottom interposer side; and
a solderless metal pillar comprising:
a top pillar end that is bonded to and directly contacts the bottom interposer circuit pattern;
a bottom pillar end that is bonded to the top substrate circuit pattern, and
a lateral pillar surface,
wherein the bottom pillar end is bonded to the top substrate circuit pattern with a solder, and at least a portion of the solder is directly vertically between the bottom pillar end and the top substrate circuit pattern, and
wherein a portion of the encapsulating material is directly below the bottom pillar end and directly vertically between the bottom pillar end and the top substrate side.
2. The semiconductor package of claim 1 , wherein the solderless metal pillar comprises a copper pillar.
3. The semiconductor package of claim 1 , wherein the lateral pillar surface bordering the bottom pillar end is free of the solder.
4. The semiconductor package of claim 1 , wherein a top end of the solder is laterally wider than a bottom end of the solder.
5. The semiconductor package of claim 1 , wherein the solder comprises a solder cap on the bottom pillar end, and wherein at least a portion of the solder cap comprises a convex surface facing toward the substrate.
6. The semiconductor package of claim 1 , wherein at least a portion of the lateral pillar surface bordering the bottom pillar end is free of the solder.
7. The semiconductor package of claim 1 , wherein the solderless metal pillar is vertically taller than the semiconductor die.
8. A method of manufacturing a semiconductor package, the method comprising:
providing a substrate comprising a top substrate side, a bottom substrate side, a plurality of lateral substrate sides between the top and bottom substrate sides, and a top substrate circuit pattern on the top substrate side;
mounting a semiconductor die on the top substrate side, the semiconductor die comprising a top die side, a bottom die side facing the top substrate side, and a plurality of lateral die sides;
forming an encapsulating material comprising a top encapsulant side and a bottom encapsulant side facing the top substrate side, where the encapsulating material encapsulates at least the lateral die sides and at least a portion of the top substrate side;
forming an interposer comprising:
a top interposer side,
a bottom interposer side facing the top encapsulant side,
a plurality of lateral interposer sides, and
a bottom interposer circuit pattern on the bottom interposer side; and
forming a solderless metal pillar comprising:
a top pillar end that is bonded to and directly contacts the bottom interposer circuit pattern,
a bottom pillar end that is bonded to the top substrate circuit pattern, and
a lateral pillar surface,
wherein the bottom pillar end is bonded to the top substrate circuit pattern with a solder, and at least a portion of the solder is directly vertically between the bottom pillar end and the top substrate circuit pattern, and
wherein a portion of the encapsulating material is directly below the bottom pillar end and directly vertically between the bottom pillar end and the top substrate side.
9. The method of claim 8 , wherein the lateral pillar surface bordering the bottom pillar end is free of the solder.
10. The method of claim 8 , wherein at least a portion of the lateral pillar surface bordering the bottom pillar end is free of the solder.