Semiconductor package structure for improving die warpage and manufacturing method thereof
A semiconductor die package includes a semiconductor die, a film for improving die warpage bonded to a first face of the semiconductor die, a plurality of electrically conductive bumps formed on a second face of the semiconductor die, a substrate onto which the electrically conductive bumps of the second face of the semiconductor die are bonded to electrically connect the semiconductor die and the substrate, and a mold compound applied these components to form an exposed surface of the semiconductor die package that is coplanar with an exposed surface of the film.
1. A method of manufacturing a semiconductor die package, the method comprising:
providing a semiconductor die having a first face, a second face opposite the first face, and a die edge face joining the first face to the second face;
providing a film having a first surface, a second surface opposite the first surface, and a film edge surface joining the first surface to the second surface, the first surface of the film bonded to and covering the first face of the semiconductor die;
providing a substrate having a top surface onto which the semiconductor die is bonded using a plurality of electrically conductive bumps on the second face of the semiconductor die;
providing one or more interconnects on the top surface of the substrate, wherein each of the one or more interconnects are symmetric about a plane:
that is substantially parallel to the top surface of the substrate; and
that intersects at substantially a midpoint of each of the one or more interconnects; and
providing a mold compound covering the substrate, the mold compound directly contacting the film edge surface and the die edge face and exposing an upper surface of the one or more interconnects,
wherein a top surface of the mold compound is coplanar with the second surface of the film, and
wherein the mold compound encompasses the one or more interconnects such that at least a portion of a top surface of the one or more interconnects does not extend beyond the top surface of the mold compound.
2. The method according to claim 1 , wherein the film has a thickness less than 20 μm.
3. The method according to claim 1 , wherein the mold compound directly covers the film edge surface and the die edge face, and wherein the second surface of the film is exposed by the mold compound.
4. The method according to claim 1 , wherein:
the second surface of the film consists of a single planar surface; and
the top surface of the mold compound is coplanar with the single planar surface of the second surface.
5. The method according to claim 1 , wherein:
the second surface of the film and the top surface of the mold compound define an upper, external surface of the semiconductor die package; and
a lower surface of the substrate defines a lower, external surface of the semiconductor die package that is opposite the upper, external surface.
6. The method according to claim 1 , wherein:
the film edge surface extends from an interface with the die edge face to an interface with the top surface of the mold compound.
7. A method of manufacturing a semiconductor die package, the method comprising:
providing a substrate having a first surface;
providing a semiconductor die having a first face, a second face opposite the first face, and a die edge face joining the first face to the second face;
bonding and electrically interconnecting the second face of the semiconductor die to the first surface of the substrate using a plurality of conductive elements;
providing a film having a first surface, a second surface opposite the first surface of the film, and a film edge surface joining the first surface of the film to the second surface of the film, the first surface of the film bonded to and covering the first face of the semiconductor die;
providing one or more interconnects on the first surface of the substrate, wherein each of the one or more interconnects are symmetric about a plane:
that is substantially parallel to the first surface of the substrate; and
that intersects at substantially a midpoint of each of the one or more interconnects; and
after providing the one or more interconnects, providing a mold compound directly contacting the first surface of the substrate, the film edge surface and the die edge face and exposing an upper surface of the one or more interconnects,
wherein a top surface of the mold compound is coplanar with the second surface of the film, and
wherein the mold compound encompasses the one or more interconnects such that at least a portion of a top surface of the one or more interconnects does not extend above the top surface of the mold compound.
8. The method according to claim 7 , wherein the film has a thickness less than 20 μm.
9. The method according to claim 7 , wherein the second face of the semiconductor die comprises one or more circuit elements electrically connected to the plurality of conductive elements.
10. The method according to claim 7 , wherein the mold compound directly covers the film edge surface, the die edge face, and the substrate, and wherein the second surface of the film is exposed by the mold compound.
11. The method according to claim 7 , wherein:
the second surface of the film consists of a single planar surface; and
the top surface of the mold compound is coplanar with the single planar surface of the second surface.
12. The method according to claim 7 , wherein:
the second surface of the film and the top surface of the mold compound define an upper, external surface of the semiconductor die package; and
a second surface of the substrate, opposite the first surface of the substrate, defines a lower, external surface of the semiconductor die package.
13. The method according to claim 7 , wherein:
the film edge surface extends from an interface with the die edge face to an interface with the top surface of the mold compound.
14. A method of manufacturing a semiconductor die package, the method comprising:
providing a semiconductor die having a first face, a second face opposite the first face, and a die edge face joining the first face to the second face;
providing a film having a first surface covering the first face of the semiconductor die, a second surface opposite the first surface, and a film edge surface joining the first surface to the second surface;
providing a substrate having a top surface onto which the semiconductor die is bonded using a plurality of conductive elements on the second face of the semiconductor die that electrically interconnect circuitry of the semiconductor die and the substrate;
providing one or more interconnects on the top surface of the substrate, wherein each of the one or more interconnects are symmetric about a plane:
that is substantially parallel to the top surface of the substrate; and
that intersects at substantially a midpoint of each of the one or more interconnects; and
providing a mold compound directly contacting and covering the film edge surface and exposing the second surface of the film opposite the first surface of the film, the mold compound exposing an upper surface of the one or more interconnects,
wherein a top surface of the mold compound is coplanar with the second surface of the film, and
wherein the mold compound encompasses the one or more interconnects such that at least a portion of a top surface of the one or more interconnects does not extend beyond the top surface of the mold compound.
15. The method according to claim 14 , wherein the second face of the semiconductor die comprises one or more circuit elements electrically connected to the plurality of conductive elements.
16. The method according to claim 14 , wherein the film has a thickness less than 20 μm.
17. The method according to claim 14 , wherein:
the second surface of the film consists of a single planar surface; and
the top surface of the mold compound is coplanar with the single planar surface of the second surface.
18. The method according to claim 14 , wherein:
the second surface of the film and the top surface of the mold compound define an upper, external surface of the semiconductor die package; and
a lower surface of the substrate defines a lower, external surface of the semiconductor die package that is opposite the upper, external surface.
19. The method according to claim 14 , wherein:
the film edge surface extends from an interface with the die edge face to an interface with the top surface of the mold compound.
20. The method according to claim 1 , wherein:
a height of the upper surface of each of the one or more interconnects is less than a height of the first face of the semiconductor die above the top surface of the substrate.
21. The method according to claim 7 , wherein:
a height of the upper surface of each of the one or more interconnects is less than a height of the first face of the semiconductor die above the first surface of the substrate.
22. The method according to claim 14 , wherein:
a height of the upper surface of each of the one or more interconnects is less than a height of the first face of the semiconductor die above the top surface of the substrate.