Method for fabricating semiconductor package and semiconductor package using the same

1. A method for fabricating a semiconductor package, the method comprising:

forming a first leadframe pattern;

encapsulating the first leadframe pattern with an encapsulant defining:

an encapsulant first surface adjacent the first leadframe pattern; and

an encapsulant second surface opposite the encapsulant first surface;

forming a conductive via extending from the encapsulant second surface to the first leadframe pattern;

forming a second leadframe pattern on the encapsulant second surface, the second leadframe pattern coupled to the first leadframe pattern through the conductive via;

etching part of the first leadframe pattern to form an etched first leadframe surface configured to receive an interconnect to a semiconductor die; and

one or both of:

forming a first solder mask on the encapsulant second surface and exposing a portion of the second leadframe pattern; and/or

forming a second solder mask on the encapsulant first surface and exposing a portion of the etched first leadframe surface.

2. The method of claim 1 , wherein:

the conductive via comprises a laser-drilled throughhole filed with conductive material.

3. The method of claim 1 , wherein:

the second leadframe pattern is formed concurrently with the conductive via.

4. The method of claim 1 , further comprising:

attaching the semiconductor die to the etched first leadframe surface through the interconnect;

wherein the interconnect comprises one or both of:

a metallic pillar; and/or

a solder.

5. The method of claim 4 , further comprising:

providing a molding encapsulant over the encapsulant first surface and around the semiconductor die.

6. The method of claim 5 , wherein:

the molding encapsulant encapsulates the interconnect between the semiconductor die and the etched first leadframe surface.

7. The method of claim 1 , wherein:

the encapsulant first surface protrudes past the etched first leadframe surface.

8. The method of claim 1 , wherein:

said forming a first leadframe pattern comprises:

forming the first leadframe pattern on a metallic frame supported by a carrier; and

said etching the first leadframe pattern comprises:

removing the carrier and the metallic frame to expose the first leadframe pattern for etching.

9. The method of claim 1 , comprising:

forming the second solder mask;

wherein the encapsulant is a molding compound.

10. A semiconductor package comprising:

a substrate comprising:

a first encapsulant;

a first leadframe pattern embedded into a top surface of the first encapsulant;

a second leadframe pattern protruding below a bottom surface of the first encapsulant; and

a conductive via connecting the first leadframe pattern to the second leadframe pattern;

a semiconductor die mounted on the substrate and electrically connected to the first leadframe pattern;

a second encapsulant over the first encapsulant and around the semiconductor die; and

a first solder mask under the substrate and exposing a portion of the second leadframe pattern;

wherein:

the first encapsulant comprises a first mold compound layer;

the second encapsulant comprises a second mold compound layer;

a thickness of the conductive via decreases from the second leadframe pattern to the first leadframe pattern;

the semiconductor die is coupled to the first leadframe pattern by conductive bumps; and

the second encapsulant encapsulates the conductive bumps between the semiconductor die and the first leadframe pattern.

11. The semiconductor package of claim 10 , comprising:

a second solder mask over the substrate and exposing a portion of the first leadframe pattern for coupling with the semiconductor die;

wherein:

the conductive via comprises a laser drilled via filled with conductive material; and

the first encapsulant protrudes past a top surface of the first leadframe pattern.

12. A semiconductor package comprising:

a substrate comprising:

a non-laminate first encapsulant;

a first leadframe pattern embedded in the first encapsulant;

a second leadframe pattern on the first encapsulant; and

a conductive via electrically connecting the first leadframe pattern to the second leadframe pattern;

a semiconductor die mounted on the substrate and electrically connected to the first leadframe pattern; and

one or both of:

a first solder mask under the substrate and exposing a portion of the second leadframe pattern; and/or

a second solder mask over the substrate and exposing a portion of the first leadframe pattern for coupling with the semiconductor die.

13. The semiconductor package of claim 12 , comprising:

the first solder mask.

14. The semiconductor package of claim 12 , comprising:

the second solder mask.

15. The semiconductor package of claim 12 , comprising:

the first and second solder masks.

16. The semiconductor package of claim 12 , wherein:

the first encapsulant comprises a molding compound; and

the conductive via comprises a laser drilled via filled with conductive material.

17. The semiconductor package of claim 12 , wherein:

a thickness of the conductive via decreases from the second leadframe pattern to the first leadframe pattern.

18. The semiconductor package of claim 12 , further comprising:

a second encapsulant over the first encapsulant and around the semiconductor die;

wherein:

the first encapsulant comprises a first mold compound layer; and

the second encapsulant comprises a second mold compound layer.

19. The semiconductor package of claim 18 , further comprising:

conductive bumps coupling the semiconductor die to the first leadframe pattern;

wherein the second encapsulant encapsulates the conductive bumps between the semiconductor die and the first leadframe pattern.

20. The semiconductor package of claim 12 , further comprising:

the first encapsulant protrudes past a top surface of the first leadframe pattern.