Encapsulated semiconductor package and method of manufacturing thereof
View Patent ↗Encapsulated semiconductor packages and methods of production thereof. As a non-limiting example, a semiconductor package may be produced by partially dicing a wafer, molding the partially diced wafer, and completely dicing the molded and partially diced wafer.
1. A semiconductor device comprising:
a semiconductor die comprising:
an active die surface;
an inactive die surface opposite the active die surface;
a plurality of side die surfaces extending between the active die surface and the inactive die surface; and
a tab extending from a first side die surface of the plurality of side die surfaces; and
an encapsulant surrounding at least the side die surfaces,
wherein an end surface of the tab is exposed from the encapsulant.
2. The semiconductor device of claim 1 , wherein the tab is centered on the first side die surface.
3. The semiconductor device of claim 1 , wherein an end surface of the tab is coplanar with a side surface of the encapsulant.
4. The semiconductor device of claim 1 , wherein the tab comprises a same height as the first side die surface.
5. The semiconductor device of claim 1 , wherein the encapsulant covers the inactive die surface and a top surface of the tab.
6. The semiconductor device of claim 1 , wherein the encapsulant extends laterally outward from each of the plurality of side die surfaces no more than 25 um.
7. The semiconductor device of claim 1 , wherein the semiconductor die comprises:
a second tab extending from a second side die surface of the plurality of side die surfaces, wherein an end surface of the second tab is exposed from the encapsulant;
a third tab extending from a third side die surface of the plurality of side die surfaces, wherein an end surface of the third tab is exposed from the encapsulant; and
a fourth tab extending from a fourth side die surface of the plurality of side die surfaces, wherein an end surface of the fourth tab is exposed from the encapsulant.
8. The semiconductor device of claim 1 , wherein:
the tab comprises a top tab side, a bottom tab side, a first lateral tab side, a second lateral tab side, and an end tab side;
the end tab side comprises a cut surface; and
each of the first and second lateral tab sides comprises an etched surface.
9. The semiconductor device of claim 1 , wherein the tab extends orthogonally from the first side die surface.
10. A semiconductor device comprising:
a semiconductor die comprising:
a top die surface;
a bottom die surface opposite the top die surface;
a plurality of lateral die surfaces extending between the top die surface and the bottom die surface; and
a tab extending from a first lateral die surface of the plurality of lateral die surfaces, the tab comprising:
a top tab surface;
a bottom tab surface opposite the top tab surface;
a first lateral tab surface;
a second lateral tab surface;
an end lateral tab surface; and
an encapsulant covering at least the first and second lateral tab surfaces, but not the end lateral tab surface.
11. The semiconductor device of claim 10 , wherein the encapsulant covers the top die surface and the top tab surface.
12. The semiconductor device of claim 10 , wherein the bottom tab surface and the bottom die surface are exposed from the encapsulant.
13. The semiconductor device of claim 10 , wherein the top tab surface is coplanar with the top die surface.
14. The semiconductor device of claim 10 , wherein the bottom tab surface is coplanar with the bottom die surface.
15. The semiconductor device of claim 10 , wherein a lateral width of the tab is less than a vertical height of the tab.
16. The semiconductor device of claim 10 , wherein the tab is laterally centered on the first lateral die surface.
17. The semiconductor device of claim 10 , wherein the end lateral tab surface comprises a cut surface, and the first and second lateral tab surfaces each comprise an etched surface.
18. A semiconductor device comprising:
a semiconductor die comprising:
a top die surface;
a bottom die surface opposite the top die surface;
a plurality of lateral die surfaces extending between the top die surface and the bottom die surface; and
a tab extending from a first lateral die surface of the plurality of lateral die surfaces, the tab comprising:
a top tab surface;
a bottom tab surface opposite the top tab surface;
a first lateral tab surface;
a second lateral tab surface;
an end lateral tab surface; and
an encapsulant covering at least the top die surface, the lateral die surfaces, the top tab surface, and the first and second lateral tab surfaces.
19. The semiconductor device of claim 18 , wherein:
the top die surface and the top tab surface are coplanar; and
the bottom die surface and the bottom tab surface are coplanar.
20. The semiconductor device of claim 18 , wherein the end lateral tab surface is exposed from the encapsulant, and the semiconductor device further comprises:
a second tab that extends from a second lateral die surface of the plurality of lateral die surfaces, wherein an end surface of the second tab is exposed from the encapsulant;
a third tab that extends from a third lateral die surface of the plurality of lateral die surfaces, wherein an end surface of the third tab is exposed from the encapsulant; and
a fourth tab that extends from a fourth lateral die surface of the plurality of lateral die surfaces, wherein an end surface of the fourth tab is exposed from the encapsulant.