Semiconductor device including leadframe with a combination of leads and lands and method
A semiconductor device includes a die pad, a plurality of first lands each having a first land first top recessed portion disposed on a first land first end distal to the die pad, and a plurality of second lands each having a second land first bottom recessed portion disposed on a second land first end distal to the die pad. A semiconductor die is electrically connected to the first and second lands. A package body, which defines a bottom surface and a side surface, at least partially encapsulating the first and second lands and the semiconductor die such that at least portions of the first and second lands are exposed in and substantially flush with the bottom surface of the package body.
1. A semiconductor device, comprising:
a die pad;
a plurality of first lands in spaced relation to the die pad, wherein each of the first lands has a first land first top recessed portion disposed on a first land first end distal to the die pad, and wherein each of the first lands has a first land second top recessed portion disposed on a first land second end proximate to the die pad;
a plurality of second lands in spaced relation to the die pad, wherein each of the second lands has a second land first bottom recessed portion disposed on a second land first end distal to the die pad;
a semiconductor die electrically coupled to the first and second lands; and
a package body defining a bottom surface and a side surface, the package body at least partially encapsulating the first and second lands and the semiconductor die such that at least portions of the first and second lands are exposed in and substantially flush with the bottom surface of the package body, wherein:
the first and second lands are positioned between the die pad and the side surface;
the second lands are positioned proximate to the side surface;
the first lands are positioned between the die pad and the second lands; and
the first land first recessed top portion of each first land and the second land first bottom recessed portion of each second land are encapsulated by the package body.
2. The semiconductor device of claim 1 , wherein each of the second lands has a second land second bottom recessed portion disposed on a second land second end proximate to the die pad.
3. The semiconductor device of claim 1 , wherein:
the die pad has multiple peripheral edge segments;
the semiconductor die is coupled to the die pad;
the plurality of first lands are segregated into at least two sets extending along respective ones of at least two peripheral edge segments of the die pad;
the plurality of second lands are segregated into at least two sets extending along respective ones of at least two peripheral edge segments of the die pad; and
the semiconductor device further comprises a plurality of third lands segregated into at least two sets extending along respective ones of at least two peripheral edge segments of the die pad in spaced relation thereto, wherein:
each of the third lands has a third land first top recessed portion disposed on a third land first end proximate to the die pad; and
the third land first top recessed portion of each third land is encapsulated by the package body.
4. The semiconductor device of claim 3 , wherein the first lands are separated from the third lands by at least one trench formed in the bottom surface of the package body.
5. The semiconductor device of claim 3 further comprising:
a plurality of fourth lands segregated into at least two sets extending along respective ones of at least two peripheral edge segments of the die pad in spaced relation thereto, wherein:
each of the fourth lands has a fourth land first bottom recessed portion disposed on a fourth land first end distal to the die pad; and
the fourth lands are generally concentrically positioned between the second lands and the third lands.
6. The semiconductor device of claim 5 , wherein each of the fourth lands has a fourth land second bottom recessed portion disposed on fourth land second end proximate to the die pad.
7. The semiconductor device of claim 3 , wherein:
the first lands are generally concentrically positioned between the third lands and the die pad such that each set of the first lands extends along a corresponding set of the third lands; and
the third lands are generally concentrically positioned between the second lands and the first lands such that each set of the third lands extends along a corresponding set of the second lands.
8. The semiconductor device of claim 7 , wherein the first lands of each set thereof are offset relative to the third lands of the corresponding set thereof.
9. The semiconductor device of claim 1 further comprising:
a tie bar comprising an inner portion and an outer portion separated from the inner portion by a gap, the inner portion attached to and extending from the die pad, the tie bar having a tie bar top surface and a tie bar bottom surface, wherein:
the tie bar top surface of the outer portion is co-planar with the die pad top surface;
a first portion of the tie bar bottom surface of the outer portion comprises a recessed surface that is half-etched; and
the first portion of the tie bar bottom surface is encapsulated by the package body.
10. The semiconductor device of claim 9 , wherein:
the die pad has a generally quadrangular configuration;
the first and second lands are segregated into at least four sets that each extend along a respective one of the peripheral edge segments of the die pad; and
a second portion of the tie bar bottom surface is co-planar with the die pad bottom surface and exposed in and substantially flush with the bottom surface of the package body.
11. The semiconductor device of claim 1 , wherein a portion of the die pad is exposed in and substantially flush with the bottom surface of the package body.
12. The semiconductor device of claim 1 , wherein the semiconductor die is electrically connected to the first and second lands by conductive wires which are covered by the package body.
13. A semiconductor device, comprising:
a generally planar die pad;
a plurality of first lands extending along peripheral edge segments of the die pad in spaced relation thereto, wherein each of the first lands has a first land first top recessed portion disposed on a first land first end distal to the die pad;
a plurality of second lands extending along peripheral edge segments of the die pad in spaced relation thereto, wherein each of the second lands has a second land first bottom recessed portion disposed on a second land first end distal to the die pad;
a semiconductor die electrically coupled to the first and second lands; and
a package body defining a generally planar bottom surface and a side surface, the package body at least partially encapsulating the first and second lands and the semiconductor die such that at least portions of the first and second lands are exposed in the bottom surface of the package body, wherein:
the first and second lands are positioned between the die pad and the side surface of the package body;
the second lands are positioned proximate to the side surface;
the first lands are positioned between the die pad and the second lands such that no portion of the first lands are positioned proximate to the side surface; and
the first land first recessed portion of each first land and the second land first bottom recessed portion of each second land are encapsulated by the package body.
14. The semiconductor device of claim 13 further comprising:
a plurality of third lands extending along peripheral edge segments of the die pad in spaced relation thereto, wherein each of the third lands has a third land first top recessed portion disposed on a third land first end proximate to the die pad, wherein:
the third land first top recessed portion of each third land is encapsulated by the package body;
the semiconductor die is electrically coupled to the third lands; and
the first lands are generally concentrically positioned between the third lands and the die pad, and the third lands are generally concentrically positioned between the second lands and the first lands.
15. The semiconductor device of claim 14 , wherein:
each of the first lands has a first land second top recessed portion disposed on a first land second end proximate to the die pad; and
each of the second lands has a second land second bottom recessed portion disposed on a second land second end proximate to the die pad.
16. The semiconductor device of claim 14 further comprising:
a plurality of fourth lands extending along peripheral edge segments of the die pad in spaced relation thereto, wherein:
each of the fourth lands has a fourth land first bottom recessed portion disposed on a fourth land first end distal to the die pad; and
the fourth lands are generally concentrically positioned between the second lands and the third lands.
17. The semiconductor device of claim 16 , wherein each of the fourth lands has a fourth land second bottom recessed portion disposed on fourth land second end proximate to the die pad.
18. The semiconductor device of claim 17 , wherein:
the plurality of first lands and the plurality of third are offset relative to each other; and
the plurality of second lands and the plurality of fourth lands are offset relative to each other.
19. The semiconductor device of claim 13 further comprising:
a tie bar comprising an inner linear portion and an outer linear portion separated from the inner linear portion by a gap, wherein:
the inner linear portion is attached to and extends from the die pad,
the outer linear portion has a bottom surface with a first portion that is generally co-planar to a bottom surface of the die pad and a second portion that is recessed such that the second portion is recessed relative to the first portion; and
the second portion of the bottom surface of the tie bar is encapsulated by the package body.
20. A semiconductor device, comprising:
a semiconductor die defining multiple peripheral edge segments;
a plurality of first lands segregated into at least two sets extending along respective ones of at least two peripheral edge segments of the semiconductor die, wherein each of the first lands has a first land first top recessed portion disposed on a first land first end distal to the die pad;
a plurality of second lands segregated into at least two sets extending along respective ones of at least two peripheral edge segments of the semiconductor die, wherein each of the second lands has a second land first top recessed portion disposed on a second land first end proximate to the die pad;
a plurality of third lands segregated into at least two sets extending along respective ones of at least two peripheral edge segments of the semiconductor die, wherein each of the third lands has a third land first bottom recessed portion disposed on a third land first end distal to the die pad; and
a package body defining a generally planar bottom surface and a side surface, the package body at least partially encapsulating the first, second, and third lands and the semiconductor die such that at least portions of the first, second, and third lands are exposed in and substantially flush with the bottom surface of the package body, wherein:
the semiconductor die is electrically coupled to the first, second, and third lands;
at least the second and third lands are positioned between the semiconductor die and the side surface of the package body; and
the first land first recessed portion of each first land, the second land first top recessed portion of each second land, and the third land first bottom recessed portion of each third land are encapsulated by the package body.