Semiconductor package lid thermal interface material standoffs
View Patent ↗Semiconductor package lid thermal interface material standoffs are disclosed and may include a substrate, a semiconductor die bonded to the substrate, a package lid bonded to the substrate and the semiconductor die thermal interface material in contact the semiconductor die, and standoffs that define a distance between the package lid and the substrate. The package lid may comprise thermal conducting material. The standoff may be within a portion of the thermal interface material. The package lid may provide a hermetic seal with the substrate. A passive device may be bonded to the substrate and covered by the package lid. A standoffs may also be formed on portions of the lid that are not in contact with the substrate. The standoff may be formed on four edges of the package lid. The standoff may comprise structures pressed into the lid.
1. A semiconductor package comprising:
a substrate;
a semiconductor die bonded to the substrate;
a package lid comprising:
a foot that is bonded to the substrate; and
a plurality of standoffs extending from the foot of the package lid and spaced around a perimeter of the foot of the package lid, and that define a distance between the package lid and the substrate, wherein the package lid is bonded to the semiconductor die; and
thermal interface material (TIM) in contact with the semiconductor die,
wherein:
the package lid bonded to the substrate provides a hermetic seal with the substrate, and
the package lid is configured such that, when stacked with a second package lid comprising a second TIM, the standoffs contact the second package lid and thereby define a gap that maintains at least the TIM separated from the second package lid or the second TIM separated from the package lid.
2. The semiconductor package according to claim 1 , wherein the package lid comprises a thermal conducting material.
3. The semiconductor package according to claim 1 , wherein at least one of the plurality of standoffs is at least partially bounded by an adhesive bonding the package lid to the substrate.
4. The semiconductor package according to claim 1 , wherein a passive device is bonded to the substrate and is covered by the package lid.
5. The semiconductor package according to claim 1 , wherein the package lid comprises another standoff that is not one of the plurality of standoffs, wherein the another standoff is also formed on one or more portions of the package lid and is not in contact with the substrate.
6. The semiconductor package according to claim 1 , wherein—one or more of the plurality of standoffs are positioned at or near a center of a respective side of the package lid.
7. The semiconductor package according to claim 1 , wherein each of the plurality of standoffs corresponds to a reciprocal indentation in the package lid reciprocal with and directly across a thickness of the package lid from the corresponding standoff.
8. A semiconductor package comprising:
a packaging substrate;
an interposer bonded directly to the packaging substrate;
a semiconductor die bonded directly to the interposer;
a package lid bonded directly to the packaging substrate and bonded directly to the semiconductor die, the package lid comprising a plurality of standoffs non-continuous to each other and spaced around a perimeter of the package lid, the plurality of standoffs being bonded directly to the packaging substrate, and wherein the plurality of standoffs comprises at least four standoffs; and
thermal interface material (TIM) bonding the package lid to the semiconductor die,
wherein the package lid is configured such that, when stacked with a second package lid comprising a second TIM, the standoffs contact the second package lid and thereby define a gap that maintains at least the TIM separated from the second package lid or the second TIM separated from the package lid.
9. The semiconductor package according to claim 8 , wherein the package lid comprises a thermal conducting material.
10. The semiconductor package according to claim 8 , wherein at least one of the plurality of standoffs is bounded on multiple sides by an adhesive that bonds the package lid to the substrate.
11. The semiconductor package according to claim 8 , wherein the package lid comprises another standoff that is not one of the plurality of standoffs, wherein the another standoff is positioned directly above the substrate and is not directly coupled to the substrate or to any electronic component.
12. The semiconductor package according to claim 8 , wherein the plurality of standoffs are formed on, at, or near one or more edges of the package lid.
13. The semiconductor package according to claim 8 , wherein at least one of the plurality of standoffs corresponds to a reciprocal indentation in the package lid reciprocal with and directly across a thickness of the package lid from the corresponding standoff.
14. A method for forming a semiconductor package, the method comprising:
bonding a semiconductor die to a packaging substrate; and
bonding a first package lid to the packaging substrate and the semiconductor die,
wherein the first package lid comprises:
thermal interface material (TIM) that is in contact with the semiconductor die;
standoffs located on and spaced around a perimeter of the first package lid, the first package lid being bonded to the semiconductor die and the packaging substrate; and
indentations reciprocal with and directly across a thickness of the first package lid from the standoffs,
wherein the first package lid is configured such that, when stacked with a second package lid comprising a second TIM, the standoffs contact the second package lid and thereby define a gap that maintains at least the first TIM separated from the second package lid or the second TIM separated from the first package lid.
15. The method according to claim 14 , wherein the first package lid comprises an inner cavity in which the semiconductor die is positioned and in which at least one of the standoffs is located.
16. The method according to claim 14 , wherein there is a gap between at least one of the standoffs and the substrate.
17. A semiconductor package comprising:
a semiconductor die bonded to a packaging substrate; and
a first package lid bonded to the packaging substrate and the semiconductor die,
wherein the first package lid comprises:
thermal interface material (TIM) that is in contact with the semiconductor die;
standoffs located on and around a perimeter of the first package lid, the first package lid being bonded to the semiconductor die and the packaging substrate; and
indentations reciprocal with and directly across a thickness of the first package lid from the standoffs,
wherein the first package lid is configured such that, when stacked with a second package lid comprising a second TIM, the standoffs contact the second package lid and thereby define a gap that maintains at least the first TIM separated from the second package lid or the second TIM separated from the first package lid.
18. The semiconductor package according to claim 17 , wherein the first package lid comprises an inner cavity in which the semiconductor die is positioned and in which at least one of the standoffs is located.
19. The semiconductor package according to claim 17 , wherein there is a gap between at least one of the standoffs and the substrate.