Semiconductor device and method of manufacturing thereof
View Patent ↗A semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a method of manufacturing a semiconductor device comprising forming interconnection structures by at least part performing a lateral plating process, and a semiconductor device manufactured thereby.
1. An electronic device comprising:
a bond pad; and
a conductive pillar on the bond pad, the conductive pillar comprising:
an inner pillar core comprising a top core surface, a bottom core surface, and a lateral core surface between the top core surface and the bottom core surface;
a seed layer that laterally surrounds the inner pillar core; and
an outer plated metal that laterally surrounds the seed layer,
wherein at least a portion of the top core surface is exposed from the seed layer.
2. The electronic device of claim 1 , wherein the entire top core surface is exposed from the seed layer.
3. The electronic device of claim 1 , comprising a second seed layer positioned laterally between the seed layer and the outer plated metal.
4. The electronic device of claim 3 , wherein at least a portion of the top core surface is exposed from the second seed layer.
5. The electronic device of claim 1 , wherein at least a portion of the top core surface is exposed from the outer plated metal.
6. The electronic device of claim 1 , wherein the inner pillar core is vertically longer than the outer plated metal.
7. An electronic device comprising:
a bond pad; and
a conductive pillar on the bond pad, the conductive pillar comprising:
an inner pillar core comprising a top core surface, a bottom core surface, and a lateral core surface between the top core surface and the bottom core surface;
a seed layer that laterally surrounds the inner pillar core; and
an outer plated metal that laterally surrounds the seed layer,
wherein a top surface of the outer plated metal is coplanar with the top core surface.
8. The electronic device of claim 7 , wherein a top surface of the seed layer is coplanar with the top core surface.
9. The electronic device of claim 7 , comprising a second seed layer positioned laterally between the seed layer and the outer plated metal, wherein a top surface of the second seed layer is coplanar with the top core surface.
10. The electronic device of claim 7 , comprising a dielectric layer that laterally surrounds the conductive pillar.
11. The electronic device of claim 10 , wherein a top surface of the dielectric layer is coplanar with the top core surface.
12. The electronic device of claim 10 , comprising a base seed layer on which the inner pillar core is plated, and wherein the dielectric layer laterally surrounds the base seed layer.
13. The electronic device of claim 7 , wherein the bottom core surface is vertically lower than a bottom surface of the outer plated metal.
14. The electronic device of claim 7 , wherein respective ends of at least four seed layers are exposed at a lateral side of the conductive pillar.
15. An electronic device comprising:
a bond pad; and
a conductive pillar on the bond pad, the conductive pillar comprising:
a base seed layer;
an inner pillar core plated on the base seed layer, the inner pillar core comprising a top core surface, a bottom core surface, and a lateral core surface between the top core surface and the bottom core surface;
at least one horizontal seed layer on base seed layer and laterally surrounding a bottom end of the inner pillar core;
at least two vertical seed layers laterally surrounding the inner pillar core; and
an outer plated metal that laterally surrounds the at least two vertical seed layers,
wherein the at least two vertical seed layers outnumber the at least one horizontal seed layer.
16. The electronic device of claim 15 , comprising a dielectric layer that laterally surrounds the at least one horizontal seed layer.
17. The electronic device of claim 16 , wherein the dielectric layer laterally surrounds the base seed layer.
18. The electronic device of claim 16 , wherein the dielectric layer laterally surrounds the entire at least two vertical seed layers.
19. The electronic device of claim 15 , wherein a first horizontal seed layer of the at least one horizontal seed layer and a first vertical seed layer of the at least two vertical seed layers are portions of a same continuous layer of metal.
20. The electronic device of claim 15 , wherein the conductive pillar comprises more seed layers directly vertically between the inner pillar core and the bond pad than vertical seed layers laterally surrounding the inner pillar core.