Semiconductor device with redistribution layers formed utilizing dummy substrates
A semiconductor device with redistribution layers formed utilizing dummy substrates is disclosed and may include forming a first redistribution layer on a first dummy substrate, forming a second redistribution layer on a second dummy substrate, electrically connecting a semiconductor die to the first redistribution layer, electrically connecting the first redistribution layer to the second redistribution layer, and removing the dummy substrates. The first redistribution layer may be electrically connected to the second redistribution layer utilizing a conductive pillar. An encapsulant material may be formed between the first and second redistribution layers. Side portions of one of the first and second redistribution layers may be covered with encapsulant. A surface of the semiconductor die may be in contact with the second redistribution layer. The dummy substrates may be in panel form. One of the dummy substrates may be in panel form and the other in unit form.
1. A semiconductor package, comprising:
a first coreless multi-layered redistribution structure;
a second coreless multi-layered redistribution structure;
a first conductive pillar comprising a proximal end electrically and mechanically coupled to a top surface of the first coreless multi-layered redistribution structure;
a second conductive pillar comprising a proximal end electrically and mechanically coupled to a bottom surface of the second coreless multi-layered redistribution structure, and a distal end electrically and mechanically coupled to a distal end of the first conductive pillar;
a semiconductor die comprising a bottom surface electrically coupled to the top surface of the first coreless multi-layered redistribution structure and positioned between the top surface of the first coreless multi-layered redistribution structure and the bottom surface of the second coreless multi-layered redistribution structure;
an encapsulating material contacting the top surface of the first coreless multi-layered redistribution structure and the bottom surface of the second coreless multi-layered redistribution structure; and
an underfill, different from the encapsulating material, contacting the bottom surface of the semiconductor die and the top surface of the first coreless multi-layered redistribution structure.
2. The semiconductor package according to claim 1 , comprising package interconnection structures coupled to the first coreless multi-layered redistribution structure at a side of the first coreless multi-layered redistribution structure opposite the semiconductor die.
3. The semiconductor package according to claim 1 , wherein the first conductive pillar extends from the first coreless multi-layered redistribution structure at least as far as a height of the semiconductor die from the first coreless multi-layered redistribution structure.
4. The semiconductor package according to claim 3 , wherein the first conductive pillar has a width of approximately 50 mm.
5. The semiconductor package according to claim 1 , wherein the semiconductor die is electrically coupled to the first coreless multi-layered redistribution structure utilizing a conductive bump with a solder cap.
6. The semiconductor package according to claim 1 , wherein a thickness of the first coreless multi-layered redistribution structure is in a range of 20 nm to 1000 nm.
7. The semiconductor package according to claim 1 , wherein the semiconductor die is in direct contact with the second coreless multi-layered redistribution structure.
8. The semiconductor package according to claim 1 , comprising a solder ball on a second surface of the first coreless multi-layered redistribution structure, where the second surface is opposite a first surface of the first coreless multi-layered redistribution structure to which the semiconductor die is coupled.
9. A semiconductor package, comprising:
a first coreless multi-layered redistribution structure comprising a first top surface, a first bottom surface opposite the first top surface, and a first side surface adjacent the first top surface and the first bottom surface;
a second coreless multi-layered redistribution structure comprising a second top surface, a second bottom surface opposite the second top surface, and a second side surface adjacent the second top surface and the second bottom surface, wherein the second coreless multi-layered redistribution structure is electrically coupled to the first coreless multi-layered structure;
a semiconductor die connected to the first coreless multi-layered structure and positioned between the first and second coreless multi-layered redistribution structures;
a conductive pillar of a single continuous material attached to the first coreless multi-layered redistribution structure and electrically and mechanically coupled to the second coreless multi-layered redistribution structure, wherein the conductive pillar extends from the first coreless multi-layered redistribution structure at least as far as a height of the semiconductor die from the first coreless multi-layered redistribution structure; and
an encapsulant between the first and second coreless multi-layered redistribution structure, wherein the encapsulant contacts at least a portion of the semiconductor die, at least a portion of the conductive pillar, at least a portion of the first top surface of the first coreless multi-layered redistribution structure, at least a portion of the second bottom surface of the second coreless multi-layered redistribution structure, and at least one side surface selected from the first side surface of the first coreless multi-layered redistribution structure and the second side surface of the second coreless multi-layered redistribution structure.
10. The semiconductor package according to claim 9 , wherein the conductive pillar spans an entire thickness of the semiconductor die.
11. The semiconductor package according to claim 9 , wherein the conductive pillar is a copper pillar.
12. The semiconductor package according to claim 9 , wherein the semiconductor die is in direct contact with the second coreless multi-layered redistribution structure.
13. The semiconductor package according to claim 9 , wherein a top surface of the encapsulant is coplanar with the second top surface.
14. The semiconductor package according to claim 1 , wherein:
the distal end of the first conductive pillar and the distal end of the second conductive pillar form an electrical connection; and
the encapsulating material contacts and surrounds the electrical connection.
15. The semiconductor package according to claim 1 , wherein the first conductive pillar and the second conductive pillar comprises a same conductive material.
16. The semiconductor package according to claim 1 , wherein:
the semiconductor die further comprises a top surface opposite the bottom surface of the semiconductor die; and
the distal end of the second conductive pillar extends past the top surface of the semiconductor die.