SINGULATED UNIT SUBSTRATE FOR A SEMICONDCUTOR DEVICE
A singulated substrate for a semiconductor device may include a singulated unit substrate comprising circuit patterns on a top surface and a bottom surface of the singulated unit substrate. A semiconductor die may be bonded to the top surface of the singulated unit substrate. An encapsulation layer may encapsulate the semiconductor die and cover the top surface of the singulated unit substrate. The side surfaces of the singulated unit substrate between the top surface and bottom surface of the singulated unit substrate may be coplanar with side surfaces of the encapsulation layer. The semiconductor die may be electrically coupled to the singulated unit substrate utilizing solder bumps. Solder balls may be formed on the circuit patterns on the bottom surface of the singulated unit substrate. An underfill material may be formed between the semiconductor die and the top surface of the singulated unit substrate.
1 . A semiconductor device comprising:
a singulated unit substrate comprising circuit patterns on a top surface and a bottom surface of the singulated unit substrate;
a semiconductor die bonded to the top surface of the singulated unit substrate;
an encapsulation layer encapsulating the semiconductor die and covering the top surface of the singulated unit substrate, wherein side surfaces of the singulated unit substrate between the top surface and bottom surface of the singulated unit substrate are cut to be coplanar with side surfaces of the encapsulation layer.
2 . The semiconductor device according to claim 1 , wherein the semiconductor die is electrically coupled to the singulated unit substrate utilizing solder bumps.
3 . The semiconductor device according to claim 1 , wherein solder balls are formed on the circuit patterns on the bottom surface of the singulated unit substrate.
4 . The semiconductor device according to claim 1 , wherein an underfill material is formed between the semiconductor die and the top surface of the singulated unit substrate.
5 . The semiconductor device according to claim 1 , wherein the singulated unit substrate comprises conductive vias that electrically couple the circuit patterns on the top surface and bottom surface of the singulated unit substrate.
6 . The semiconductor device according to claim 1 , wherein the circuit patterns on the top surface and bottom surface of the singulated unit substrate are separated by a dielectric layer.
7 - 14 . (canceled)
15 . A semiconductor device comprising:
a singulated unit substrate comprising circuit patterns on a top surface and a bottom surface of the singulated unit substrate;
a semiconductor die bonded to the top surface of the singulated unit substrate;
an encapsulant film between the semiconductor die and the singulated unit substrate; and
a preimpregnated material (pre-preg) encapsulating the semiconductor die,
wherein side surfaces of the singulated unit substrate between the top surface and bottom surface of the singulated unit substrate are cut to be coplanar with side surfaces of the encapsulant film and the pre-preg.
16 . The semiconductor device according to claim 15 , wherein the semiconductor die is electrically coupled to the singulated unit substrate utilizing solder bumps.
17 . The semiconductor device according to claim 15 , wherein solder balls are formed on the circuit patterns on the bottom surface of the singulated unit substrate.
18 . The semiconductor device according to claim 15 , wherein an underfill material is formed between the semiconductor die and the top surface of the singulated unit substrate.
19 . The semiconductor device according to claim 15 , wherein the singulated unit substrate comprises conductive vias that electrically couple the circuit patterns on the top surface and bottom surface of the singulated unit substrate.
20 . The semiconductor device according to claim 15 , wherein the circuit patterns on the top surface and bottom surface of the singulated unit substrate are separated by a dielectric layer.
21 . A semiconductor device comprising:
a singulated unit substrate comprising circuit patterns on a top surface and a bottom surface of the singulated unit substrate;
a semiconductor die bonded to the top surface of the singulated unit substrate;
an underfill between the semiconductor die and the singulated unit substrate; and
an encapsulating material encapsulating the underfill and the top surface of the singulated unit substrate,
wherein side surfaces of the singulated unit substrate between the top surface and bottom surface of the singulated unit substrate are coplanar with side surfaces of the encapsulating material.
22 . The semiconductor device of claim 21 , comprising interconnection structures that electrically connect the semiconductor die to the singulated unit substrate, and wherein the interconnection structures are encapsulated by the underfill.
23 . The semiconductor device of claim 21 , wherein the underfill and the encapsulating material are the same material.
24 . The semiconductor device of claim 21 , wherein the side surfaces of the singulated unit substrate are water-cut to be coplanar with the side surfaces of the encapsulating material.
25 . The semiconductor device of claim 21 , wherein the circuit patterns on the top and bottom surfaces of the singulated unit substrate are separated by at least a dielectric layer, and the singulated unit substrate comprises conductive vias that electrically couple the circuit patterns on the top and bottom surfaces of the singulated unit substrate.
26 . The semiconductor device of claim 21 , comprising a second encapsulating material that encapsulates the semiconductor die and the encapsulating material.
27 . The semiconductor device of claim 26 , wherein the encapsulating material comprises an encapsulant film, and the second encapsulating material comprises a preimpregnated material (pre-preg).
28 . The semiconductor device of claim 26 , wherein the second encapsulating material completely surrounds side and top surfaces of the semiconductor die.