Semiconductor device and manufacturing method thereof
An electronic device and a method of manufacturing an electronic device. As non-limiting examples, various aspects of this disclosure provide various methods of manufacturing electronic devices, and electronic devices manufactured thereby, that comprise utilizing metal studs to further set a semiconductor die into the encapsulant.
1. A semiconductor device comprising:
a first semiconductor die having a first top die side, a first bottom die side comprising a first bond pad, and first lateral die sides between the first top and first bottom die sides;
a first dielectric layer (DL) having a first top DL side coupled to the first bottom die side, a first bottom DL side, and first lateral DL sides between the first top and first bottom DL sides;
a first metal post having a first top post side attached to the first bond pad, a first bottom post side, and a first lateral post surface between the first top and first bottom post sides, where the first metal post extends vertically through the first dielectric layer from the first bond pad to the first bottom DL side;
a second semiconductor die having a second top die side, a second bottom die side comprising a second bond pad, and second lateral die sides between the second top and second bottom die sides;
a second dielectric layer (DL) having a second top DL side coupled to the second bottom die side, a second bottom DL side, and second lateral DL sides between the second top and second bottom DL sides;
a second metal post having a second top post side attached to the second bond pad, a second bottom post side, and a second lateral post surface between the second top and second bottom post sides, where the second metal post extends vertically through the second dielectric layer from the second bond pad to the second bottom DL side; and
an encapsulating material contacting and surrounding the first and second lateral die sides and the first and second lateral DL sides, the encapsulating material having a top encapsulant side, a bottom encapsulant side, and lateral encapsulant sides between the top and bottom encapsulant sides,
wherein:
the first DL has a first DL thickness, and the second DL has a second DL thickness greater than the first DL thickness; and
the first semiconductor die has a first die thickness, and the second semiconductor die has a second die thickness less than the first die thickness.
2. The semiconductor device of claim 1 , wherein the encapsulating material covers the first top die side and/or the second top die side.
3. The semiconductor device of claim 1 , wherein the first semiconductor die comprises a first die passivation layer having a bottom side coupled to the first top DL side.
4. The semiconductor device of claim 3 , wherein the first bottom post side is coplanar with the second bottom post side, the first bottom DL side, and the second bottom DL side.
5. The semiconductor device of claim 1 , wherein a first of the first lateral DL sides and a first of the second lateral DL sides are generally parallel and laterally separated by only the encapsulating material.
6. The semiconductor device of claim 1 , comprising a first die passivation layer that covers a portion of a bottom side of the first bond pad, and wherein a portion of the first dielectric layer is directly laterally between the first metal post and the first die passivation layer.
7. The semiconductor device of claim 1 , wherein the top encapsulant side comprises a groove outside the footprints of the first and second semiconductor dies.