Plating structure for wafer level packages
View Patent ↗A plating structure for wafer level packages are disclosed and may include a semiconductor wafer comprising a plurality of semiconductor die and a plating structure for forming an under bump metal on redistribution layers on the plurality of semiconductor die. The plating structure may comprise a plating connection line around a periphery of the semiconductor wafer, and a plating bar coupling the plating connection line to plating traces on the plurality of semiconductor die. The plating traces may be electrically coupled to the redistribution layers on the plurality of semiconductor die. The semiconductor wafer may comprise a reconstituted wafer of said semiconductor die. The semiconductor wafer may comprise a wafer prior to singulating the plurality of semiconductor die. The plating bar may be located in a sawing line for the singulating of the plurality of semiconductor die. A passivation layer may cover the redistribution layer and the plating traces.
1. A semiconductor device comprising:
a semiconductor die comprising a passivation layer and a bonding pad exposed by an opening in the passivation layer;
a patterned seed layer formed on the exposed bonding pad and passivation layer;
a redistribution layer and a plating structure formed on the patterned seed layer, wherein the plating structure comprises a plating trace extending to an edge of the semiconductor die;
a second passivation layer formed on the redistribution layer and the plating structure; and
an under bump metal formed on an exposed portion of the redistribution layer utilizing the plating structure.
2. The semiconductor device according to claim 1 , comprising a reconstituted wafer of a plurality of said semiconductor die.
3. The semiconductor device according to claim 1 , wherein the plating trace is configured to reach a plating bar at the edge of the semiconductor die.
4. The semiconductor device according to claim 3 , wherein the edge of the semiconductor die extends along a sawing line of the plating bar.
5. The semiconductor device according to claim 1 , wherein the second passivation layer extends to the under bump metal.
6. The semiconductor device according to claim 5 , wherein the under bump metal is formed in an opening in the second passivation layer.
7. The semiconductor device according to claim 1 , wherein the plating structure comprises an electrode terminal for a plating process for forming the under bump metal.
8. The semiconductor device according to claim 1 , wherein the under bump metal comprises one or more of nickel, gold, and copper.
9. The semiconductor device according to claim 1 , wherein an input/output terminal is formed on the under bump metal.
10. The semiconductor device according to claim 9 , wherein the input/output terminal comprises a solder bump.
11. A method for a semiconductor device, the method comprising:
forming a patterned seed layer on an exposed bonding pad and passivation layer on a semiconductor die singulated from a semiconductor wafer;
forming a redistribution layer and a plating structure on the patterned seed layer, wherein the plating structure comprises a plating trace extending to an edge of the die;
forming a second passivation layer on the redistribution layer and the plating structure; and
forming an under bump metal on an exposed portion of the redistribution layer utilizing the plating structure.
12. The method according to claim 11 , wherein the semiconductor wafer comprises a plurality of semiconductor die and the plating structure comprises a plating connection line around a periphery of the semiconductor wafer and a plating bar coupling the plating connection line to plating traces on the plurality of semiconductor die.
13. The method according to claim 12 , wherein the plating traces are configured to reach a plating bar at the edge of the semiconductor die.
14. The method according to claim 13 , wherein the edge of the semiconductor die extends along a sawing line of the plating bar.
15. The method according to claim 11 , comprising forming the under bump metal utilizing the plating structure as an electrode terminal in a plating process.
16. The method according to claim 11 , comprising forming the under bump metal in an opening formed in the second passivation layer.
17. The method according to claim 11 , wherein the under bump metal comprises one or more of nickel, gold, and copper.
18. The method according to claim 11 , comprising forming an input/output terminal on the under bump metal.
19. The method according to claim 18 , wherein the input/output terminal comprises a solder bump.
20. A semiconductor device comprising:
a semiconductor wafer comprising a plurality of semiconductor die, said semiconductor wafer comprising a plating structure for forming an under bump metal on redistribution layers on the plurality of semiconductor die, wherein the plating structure is a plating process electrode terminal and comprises:
a plating connection line around a periphery of the semiconductor wafer; and
a plating bar coupling the plating connection line to plating traces on the plurality of semiconductor die, wherein the plating traces are electrically coupled to the redistribution layers on the plurality of semiconductor die.