CAPACITOR OF SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR MANUFACTURING THE SAME

1 . A semiconductor integrated circuit, comprising:

a substrate comprising a substrate coefficient of thermal expansion (CTE); and

a capacitor on the substrate and comprising:

a lower seed layer on a topmost substrate surface of the substrate and comprising a lower seed CTE;

a lower electrode layer on the lower seed layer and comprising a lower electrode CTE;

a buffer layer on the lower electrode layer and comprising a buffer CTE;

a dielectric layer on the buffer layer and comprising a dielectric CTE;

an upper seed layer on the dielectric layer and comprising an upper seed CTE; and

an upper electrode layer on the upper seed layer and comprising an upper electrode CTE;

wherein:

the lower electrode CTE is greater than the buffer CTE;

the buffer CTE is greater than the dielectric CTE;

the lower electrode CTE is greater than the lower seed CTE;

the lower seed CTE is greater than the substrate CTE;

the upper electrode CTE is greater than the upper seed CTE;

the upper seed CTE is greater than the dielectric CTE; and

a difference between the lower electrode CTE and the buffer CTE is greater than a difference between the buffer CTE and the dielectric CTE.

2 . The semiconductor integrated circuit of claim 1 , wherein:

the substrate comprises one or both of a semiconductor material and/or a glass material;

each layer of the capacitor is formed on the substrate;

materials of the lower seed layer, of the buffer layer, and of the upper seed layer are the same as each other;

the lower seed layer comprises a plated layer onto the topmost substrate surface;

the lower electrode layer comprises a plated layer plated onto the lower seed layer;

the buffer layer comprises a sputtered layer sputtered onto the lower electrode layer;

the dielectric layer comprises a chemical vapor deposition layer deposited onto the buffer layer;

the upper seed layer comprises a plated layer plated onto the dielectric layer; and

the upper electrode layer comprises a plated layer plated onto the upper seed layer.

3 . A semiconductor integrated circuit, comprising:

a substrate; and

a capacitor on the substrate and comprising:

a lower electrode layer coupled to the substrate and comprising a lower electrode coefficient of thermal expansion (CTE);

a buffer layer on the lower electrode layer and comprising a buffer CTE;

a dielectric layer on the buffer layer and comprising a dielectric CTE; and

an upper electrode layer on the dielectric layer;

wherein:

the lower electrode CTE is greater than the buffer CTE; and

the buffer CTE is greater than the dielectric CTE.

4 . The semiconductor integrated circuit of claim 3 , wherein:

the buffer layer comprises one or more of:

titanium-tungsten (TiW), titanium (Ti), chrome (Cr), and/or tungsten (W).

5 . The semiconductor integrated circuit of claim 3 , wherein:

the dielectric layer comprises one or more of:

silicon nitride (SiN), aluminum oxide (Al2O3), and/or hafnium oxide (HfO3).

6 . The semiconductor integrated circuit of claim 3 , wherein:

each layer of the capacitor is formed on the substrate.

7 . The semiconductor integrated circuit of claim 3 , wherein:

the substrate comprises one or both of a semiconductor material and/or a glass material.

8 . The semiconductor integrated circuit of claim 3 , wherein:

a difference between the lower electrode CTE and the buffer CTE is greater than a difference between the buffer CTE and the dielectric CTE.

9 . The semiconductor integrated circuit of claim 3 , comprising:

a lower seed layer between the substrate and the lower electrode layer and comprising a lower seed CTE;

wherein:

the lower electrode CTE is greater than the lower seed CTE; and

the lower seed CTE is greater than a CTE of the substrate.

10 . The semiconductor integrated circuit of claim 9 , wherein:

materials of the lower seed layer and of the buffer layer are the same as each other.

11 . The semiconductor integrated circuit of claim 9 , comprising:

an upper seed layer between the dielectric layer and the upper electrode layer and comprising an upper seed CTE;

wherein:

the upper electrode CTE is greater than the upper seed CTE; and

the upper seed CTE is greater than the dielectric CTE.

12 . The semiconductor integrated circuit of claim 11 , wherein:

materials of the lower seed layer, of the buffer layer, and of the upper seed layer are the same as each other.

13 . The semiconductor integrated circuit of claim 3 , wherein:

the buffer layer comprises a sputtered layer sputtered onto the lower electrode layer.

14 . A method of manufacturing a capacitor for a semiconductor integrated circuit, the method comprising:

providing a substrate; and

forming a capacitor on the substrate, said forming comprising:

forming a lower electrode layer on the substrate;

forming a buffer layer on the lower electrode layer;

forming a dielectric layer on the buffer layer; and

forming an upper electrode layer on the second seed layer;

wherein:

the lower electrode CTE of the lower electrode layer is greater than a buffer CTE of the buffer layer; and

the buffer CTE is greater than a dielectric CTE of the dielectric layer.

15 . The method of claim 14 , wherein:

the buffer layer is sputtered onto the lower electrode layer and comprises one or more of titanium-tungsten (TiW), titanium (Ti), chrome (Cr), and/or tungsten (W).

16 . The method of claim 14 , wherein:

the dielectric layer is formed by chemical vapor deposition onto the buffer layer and comprises one or more of silicon nitride (SiN), aluminum oxide (Al2O3), and/or hafnium oxide (HfO3).

17 . The method of claim 14 , wherein:

forming the capacitor comprises plating a lower seed layer on the substrate; and

forming the lower electrode layer comprises plating the lower electrode layer on the lower seed layer.

18 . The method of claim 17 , wherein:

forming the capacitor comprises plating an upper seed layer on the dielectric layer; and

forming the upper electrode layer comprises plating the upper electrode layer on the upper seed layer.

19 . The method of claim 18 , wherein:

a material of the buffer layer is same as at least one of:

a material the upper seed layer; or

a material of the lower seed layer.

20 . The method of claim 1 , wherein:

forming the lower electrode layer comprises:

forming the lower electrode layer above a topmost surface of the substrate.