Semiconductor device having conductive pads to prevent solder reflow
View Patent ↗A semiconductor device has a substrate having a plurality of conductive pads formed thereon. A semiconductor die is provided having a plurality of conductive pillars formed thereon. A solder is used for electrically coupling the conductive pillars to the conductive pads. Solder mask is formed on portions of the conductive pads to prevent the solder from flowing in an unwanted direction on the conductive pads.
1. A semiconductor device comprising:
a plurality of conductive pads formed on a substrate;
a plurality of conductive pillars formed on a semiconductor die;
a solder electrically coupling the plurality of conductive pillars to the plurality of conductive pads; and
a solder masking portion formed in the plurality of conductive pads to prevent the solder from flowing in an unwanted direction on the plurality of conductive pads, wherein at least one conductive pillar of the plurality of conductive pillars has an elliptical cross-section with a minor axis length X and a major axis length Y, and a depth of the solder masking portion is defined as X*(1/10)≦W 1 ≦X*(1/5).
2. The semiconductor device of claim 1 , wherein the solder masking portion comprises a region of reduced width of the plurality of conductive pads.
3. The semiconductor device of claim 2 , wherein the solder masking portion comprises grooves in the plurality of conductive pads.
4. The semiconductor device of claim 2 , wherein the solder masking portion is formed symmetrically on both sides of the plurality of conductive pads.
5. The semiconductor device of claim 1 , wherein the solder masking portion is formed in the plurality of conductive pads separated from one side of the plurality of conductive pillars and formed to reduce a width of the plurality of conductive pads.
6. The semiconductor device of claim 1 , wherein the plurality of conductive pillars have elliptical cross-sections.
7. The semiconductor device of claim 6 , wherein a major axis of the plurality of conductive pillars is parallel to that of the plurality of conductive pads.
8. The semiconductor device of claim 1 , wherein the solder masking portion is separated from both sides of the plurality of conductive pillars and comprises a region of reduced width of the plurality of conductive pads.
9. The semiconductor device of claim 8 , wherein the solder masking portion is a neck-down portion formed on the plurality of conductive pads.
10. The semiconductor device of claim 1 , wherein the solder comprises:
a plating solder formed on the plurality of conductive pads; and
a solder cap formed on the plurality of conductive pillars.
11. The semiconductor device of claim 1 , wherein the substrate further comprises a passivation layer having a window through which the plurality of conductive pads are exposed.
12. A semiconductor device comprising:
a plurality of conductive pads formed on a substrate;
a plurality of conductive pillars formed on a semiconductor die;
a solder electrically coupling the plurality of conductive pillars to the plurality of conductive pads; and
a solder masking portion formed in the plurality of conductive pads to prevent the solder from flowing in an unwanted direction on the plurality of conductive pads, wherein at least one conductive pillar of the plurality of conductive pillars has an elliptical cross-section with a minor axis length X and a major axis length Y, and a depth of the solder masking portion defined as X*(1/10)≦W 1 ≦X*(1/5) a distance by which the solder masking portion is separated from the at least one conductive pillar of the plurality of conductive pillars is defined as Y*(1/2)≦H 1 ≦Y.
13. The semiconductor device of claim 12 , wherein the solder masking portion comprises a region of reduced width of the plurality of conductive pads.
14. The semiconductor device of claim 12 , wherein the solder masking portion is formed in the plurality of conductive pads separated from one side of the plurality of conductive pillars and formed to reduce a width of the plurality of conductive pads.
15. The semiconductor device of claim 14 , wherein the solder masking portion comprises grooves in the plurality of conductive pads.
16. The semiconductor device of claim 14 , wherein the solder masking portion is formed symmetrically on both sides of the plurality of conductive pads.
17. A semiconductor device comprising:
a plurality of conductive pads formed on a substrate;
a plurality of conductive pillars formed on a semiconductor die;
a solder electrically coupling the plurality of conductive pillars to the plurality of conductive pads; and
a solder masking portion formed in the plurality of conductive pads to prevent the solder from flowing in an unwanted direction on the plurality of conductive pads, wherein when at least one of the plurality of conductive pillars has an elliptical cross-section with a minor axis length X and a major axis length Y, then a depth of the solder masking portion is defined as X*(1/5)≦W 2 ≦X*(1/2) and a distance by which the solder masking portion is separated from the plurality of conductive pillars is defined as Y*(5/4)≦H 2 ≦Y*(3/2).
18. The semiconductor device of claim 17 , wherein the solder masking portion comprises a region of reduced width of the plurality of conductive pads.
19. The semiconductor device of claim 17 , wherein the solder masking portion is formed in the plurality of conductive pads separated from one side of the plurality of conductive pillars and formed to reduce a width of the plurality of conductive pads.
20. The semiconductor device of claim 19 , wherein the solder masking portion comprises grooves in the plurality of conductive pads.