Encapsulated semiconductor package

1. An integrated circuit package, comprising:

a laminate comprising:

a first laminate surface;

a second laminate surface opposite the first laminate surface; and

a plurality of side laminate surfaces connecting the first laminate surface and the second laminate surface;

an integrated circuit die comprising:

a first die surface;

a second die surface opposite the first die surface and coupled to the first laminate surface;

a plurality of side die surfaces connecting the first die surface and the second die surface; and

a bond pad on the first die surface;

an encapsulant that surrounds and contacts at least the first die surface and the plurality of side die surfaces, wherein the encapsulant is a single continuous encapsulating material that comprises:

a first encapsulant surface;

a second encapsulant surface opposite the first encapsulant surface and coupled to the first laminate surface; and

a plurality of side encapsulant surfaces connecting the first encapsulant surface and the second encapsulant surface,

wherein each of the plurality of side encapsulant surfaces is coplanar with a respective one of the plurality of side laminate surfaces;

a metal column comprising:

a first column end exposed from the first encapsulant surface;

a second column end coupled to the bond pad; and

a middle column portion that extends through the encapsulant between the first column end and the second column end; and

a redistribution structure formed on the first encapsulant surface, the redistribution structure comprising:

a plurality of build-up dielectric layers;

a ball pad outside a footprint of the integrated circuit die; and

a trace within the plurality of build-up dielectric layers, where the trace extends between the metal column within the footprint of the integrated circuit die and the ball pad and electrically couples the ball pad to the first column end.

2. The integrated circuit package of claim 1 , wherein no conductors are exposed at the side laminate surfaces.

3. The integrated circuit package of claim 1 , wherein the redistribution structure comprises:

a first redistribution structure surface;

a second redistribution structure surface opposite the first redistribution structure surface, and coupled to the first encapsulant surface; and

a plurality of side redistribution structure surfaces connecting the first redistribution structure surface and the second redistribution structure surface,

wherein each of the plurality of side redistribution structure surfaces is coplanar with a respective one of the plurality of side encapsulant surfaces and with a respective one of the side laminate surfaces.

4. The integrated circuit package of claim 1 , wherein the trace directly contacts and is sandwiched between two of the plurality of build-up dielectric layers.

5. The integrated circuit package of claim 1 , wherein the metal column comprises plated metal having a maximum width that is wider than a width of the bond pad.

6. The integrated circuit package of claim 1 , wherein at least a portion of the middle column portion of the metal column is tapered.

7. The integrated circuit package of claim 6 , wherein the first column end is wider than the second column end.

8. The integrated circuit package of claim 1 , wherein at least a portion of the middle column portion of the metal column is cylindrical.

9. The integrated circuit package of claim 1 , wherein the first column end is coplanar with the first encapsulant surface.

10. The integrated circuit package of claim 1 , wherein each of the plurality of build-up dielectric layers is formed of a dielectric material other than a photo-sensitive material.

11. The integrated circuit package of claim 1 , comprising conductive balls coupled to the second laminate surface, and wherein in a cross-sectional view of the integrated circuit package, a majority of conductive balls coupled to the second laminate surface are entirely outside a footprint of the integrated circuit die.

12. An integrated circuit package, comprising:

a package layer comprising a first package layer surface on a top side of the package layer and a plurality of perimeter package layer surfaces bordering the first package layer surface;

an integrated circuit die coupled to the first package layer surface, and comprising:

a first die surface on a top side of the integrated circuit die;

a plurality of perimeter die surfaces bordering the first die surface; and

a bond pad on the first die surface;

an encapsulant that surrounds at least the first die surface and the plurality of perimeter die surfaces, and comprises a first encapsulant surface on a top side of the encapsulant and a plurality of perimeter encapsulant surfaces bordering the first encapsulant surface;

a metal column passing through the encapsulant, and comprising a first column end exposed from the encapsulant and a second column end coupled to the bond pad, wherein the metal column has a maximum width that is wider than a width of the bond pad;

a first build-up dielectric layer (DL) coupled to the encapsulant, the first build-up dielectric layer comprising a first DL side on a top side of the first build-up DL and a second DL side opposite the first DL side;

an aperture in the first build-up dielectric layer extending directly between the first DL side and the second DL side, the aperture causing at least a portion of the first column end to be uncovered by the first build-up dielectric layer;

a trace coupled to the first build-up dielectric layer, wherein at least a portion of the trace is in the aperture and coupled to the metal column through the aperture, and the trace extends away from the metal column in a direction parallel to the first encapsulant surface; and

a conductive pad coupled to the trace.

13. The integrated circuit package of claim 12 , comprising a second build-up dielectric layer coupled to the first build-up dielectric layer, wherein the second build-up dielectric layer covers and contacts the trace.

14. The integrated circuit package of claim 13 , comprising a second aperture in the second build-up dielectric layer that exposes the conductive pad through the second build-up dielectric layer, and wherein:

the conductive pad is positioned entirely outside a footprint of the integrated circuit die;

the trace is positioned both inside and outside the footprint of the integrated circuit die; and

the conductive pad comprises a solder ball pad.

15. The integrated circuit package of claim 12 , wherein each of the plurality of perimeter package layer surfaces is coplanar with a respective one of the perimeter encapsulant surfaces.

16. The integrated circuit package of claim 15 , wherein each of the plurality of perimeter package layer surfaces is coplanar with a respective side surface of the first build-up dielectric layer.

17. The integrated circuit package of claim 12 , wherein the package layer comprises a laminate coupled to the encapsulant and to the integrated circuit die.

18. The integrated circuit package of claim 12 , wherein the package layer comprises an insulative film layer.

19. An integrated circuit package, comprising:

an electronic component comprising a first component surface and a plurality of perimeter component surfaces bordering the first component surface;

an encapsulant that surrounds at least the first component surface and the plurality of perimeter component surfaces, and comprises a first encapsulant surface on a top side of the encapsulant and a plurality of perimeter encapsulant surfaces bordering the first encapsulant surface;

a conductive column passing through the encapsulant, and comprising a first column end exposed from the encapsulant and a second column end coupled to the first component surface;

a first build-up dielectric layer (DL) coupled to the encapsulant, wherein the first build-up DL comprises a center DL portion directly above a center portion of the encapsulant and having a center vertical DL thickness, and a peripheral DL portion at a periphery of the encapsulant and having a peripheral vertical thickness that is substantially different from the center vertical thickness;

a trace over the encapsulant, wherein the trace contacts the first build-up dielectric layer, and is electrically coupled to the first column end, and wherein the trace extends laterally from the first column end toward a lateral outer edge of the integrated circuit package; and

a conductive attachment pad coupled to the trace.

20. The integrated circuit package of claim 19 , wherein the first build-up dielectric layer covers at least a portion of at least one of the perimeter encapsulant surfaces.