Electronic component package fabrication method and structure
View Patent ↗A redistribution pattern is formed on active surfaces of electronic components while still in wafer form. The redistribution pattern routes bond pads of the electronic components to redistribution pattern terminals on the active surfaces of the electronic components. The bond pads are routed to the redistribution pattern terminals while still in wafer form, which is a low cost and high throughput process, i.e., very efficient process.
1. An electronic component package comprising:
an electronic component comprising an active surface that comprises or has bond pads thereon;
a redistribution pattern coupled to the active surface and electrically coupled to the bond pads, where the entire redistribution pattern is coupled to the active surface;
a buildup dielectric layer coupled to the redistribution pattern; and
a buildup circuit pattern coupled to the buildup dielectric layer, the buildup circuit pattern electrically coupled to the redistribution pattern through apertures of the buildup dielectric layer.
2. The electronic component package of claim 1 , further comprising a package body enclosing at least an inactive surface and sides of the electronic component, wherein the package body comprises a first surface parallel to and coplanar with the redistribution pattern.
3. The electronic component package of claim 1 , further comprising:
an outer dielectric layer coupled to the buildup circuit pattern; and
package connection structures electrically coupled to the buildup circuit pattern through apertures of the outer dielectric layer.
4. The electronic component package of claim 1 , comprising a redistribution pattern dielectric layer (RPDL), and wherein:
the redistribution pattern is mechanically coupled to the active surface through at least the RPDL; and
the redistribution pattern is electrically coupled to the bond pads through at least apertures in the RPDL.
5. The electronic component package of claim 1 , wherein the buildup circuit pattern comprises traces comprising lands.
6. The electronic component package of claim 5 , wherein the buildup circuit pattern comprises an electrically conductive plane.
7. An electronic component assembly comprising:
a semiconductor die comprising a first surface that comprises or has bond pads thereon, the first surface having a perimeter;
a first layer of conductive traces electrically coupled to the bond pads through apertures in at least a first insulating layer, where the entirety of said first layer of conductive traces is positioned within an area bounded by the perimeter of the first surface; and
a second layer of conductive traces electrically coupled to the first layer of conductive traces through apertures in at least a second insulating layer, where said second layer of conductive traces comprises traces that extend beyond the area bounded by the perimeter of the first surface.
8. The electronic component assembly of claim 7 , where said semiconductor die is mechanically coupled to other semiconductor die in a wafer, and the perimeter of the first surface is defined by singulation streets.
9. The electronic component assembly of claim 7 , wherein said semiconductor die is singulated from a wafer, and the perimeter of the first surface is defined by side surfaces of the semiconductor die.
10. The electronic component package of claim 7 , further comprising a package body enclosing at least a second surface and sides of the semiconductor die.
11. The electronic component package of claim 7 , wherein the package body comprises a first surface parallel to and coplanar with the redistribution pattern.
12. The electronic component package of claim 7 , wherein said first layer of conductive traces is electrically coupled to the bond pads through apertures in only the first insulating layer.
13. The electronic component package of claim 7 , wherein said second layer of conductive traces is electrically coupled to the first layer of conductive traces through apertures in only the second insulating layer.
14. An electronic component assembly comprising:
a semiconductor die comprising an active surface that comprises or has bond pads thereon, the active surface having a perimeter;
a redistribution pattern dielectric layer (RPDL) coupled to the active surface; and
a redistribution pattern coupled to the RPDL and electrically coupled to the bond pads through apertures in the RPDL, where the entire redistribution pattern is positioned within an area bounded by the perimeter of the active surface.
15. The electronic component assembly of claim 14 , where said semiconductor die is mechanically coupled to other semiconductor die in a wafer, and the perimeter of the active surface is defined by singulation streets.
16. The electronic component assembly of claim 14 , wherein said semiconductor die is singulated from a wafer, and the perimeter of the active surface is defined by side surfaces of the semiconductor die.
17. The electronic component assembly of claim 14 , comprising:
a buildup dielectric layer coupled to the redistribution pattern; and
a buildup circuit pattern coupled to the buildup dielectric layer, the buildup circuit pattern electrically coupled to the redistribution pattern through apertures in the buildup dielectric layer.
18. The electronic component package of claim 14 , further comprising a package body enclosing at least a second surface and sides of the semiconductor die, wherein the package body comprises a first surface parallel to and coplanar with the redistribution pattern.
19. The electronic component package of claim 14 , wherein the RPDL is formed on the active surface.
20. The electronic component package of claim 19 , wherein the redistribution pattern is formed on the RPDL.