Method of forming a plurality of electronic component packages
View Patent ↗A method of forming a plurality of electronic component packages includes attaching electronic components to a carrier, wherein high aspect ratio spaces exist between the electronic components. A dielectric sheet is laminated around the electronic components thus filling the spaces and forming a package body. The spaces are completely and reliably filled by the dielectric sheet and thus the package body has an absence of voids. Further, an upper surface of the package body is planar, i.e., has an absence of ripples or other non-uniformities. Further, lamination of the dielectric sheet is performed with a low cost lamination system.
1. A method of forming an electronic component package, the method comprising:
attaching electronic components having height dimensions of at least 400 micrometers (μm) to a carrier, where the attached electronic components are integrated circuit (IC) chips that each have a width dimension in a first direction greater than a respective height dimension and that are spaced no more than 100 μm apart in the first direction;
laminating a dielectric sheet around and over the electronic components, said laminating comprising:
filling the spaces between the attached electronic components with the dielectric sheet; and
pressing the dielectric sheet onto the electronic components and simultaneously heating the dielectric sheet to cause the dielectric sheet to flow around the electronic components,
wherein the dielectric sheet forms a package body enclosing the electronic components, where the package body comprises a first thickness for those portions of the package body in the spaces between the electronic components, and a second thickness, less than the first thickness, for those portions of the package body over the attached electronic components;
removing the carrier;
attaching a buildup dielectric layer directly to a respective active surface of each of the electronic components and to the package body;
forming a circuit pattern on the buildup dielectric layer; and
cutting at least the package body and the buildup dielectric layer to singulate the electronic component package.
2. The method of claim 1 further comprising:
attaching an adhesive to the carrier;
wherein the attaching electronic components to a carrier comprises temporarily attaching the electronic components to the adhesive.
3. The method of claim 1 , comprising:
forming a second buildup dielectric layer on the buildup dielectric layer and the circuit pattern;
forming a second circuit pattern on the second buildup dielectric layer that is electrically connected to the circuit pattern; and
attaching a package interconnection structure to the second circuit pattern at a location directly beneath one of the integrated circuit chips.
4. The method of claim 1 , comprising after said laminating, cutting the dielectric sheet to conform to a shape of the carrier.
5. The method of claim 1 , comprising after said attaching a buildup dielectric layer, forming a via aperture through the attached buildup dielectric layer.
6. A method of forming an electronic component package, the method comprising:
attaching electronic components having height dimensions of at least 400 micrometers (μm) to a carrier, where the attached electronic components are integrated circuit (IC) chips that each have a width dimension in a first direction greater than a respective height dimension and that are spaced no more than 100 μm apart in the first direction;
laminating a dielectric sheet around the electronic components, said laminating comprising pressing the dielectric sheet onto the electronic components and simultaneously heating the dielectric sheet to cause the dielectric sheet to flow around the electronic components, wherein the dielectric sheet forms a package body around the electronic components, and the package body encloses inactive surfaces and sides of the electronic components, the package body comprising:
a first planar surface; and
a second surface attached to an adhesive, the second surface being coplanar with a respective active surface of each of the electronic components,
wherein the package body comprises a first thickness for those portions of the package body in spaces between the electronic components and a second thickness, less than the first thickness, for those portions of the package body over the electronic components.
7. The method of claim 6 wherein said attaching electronic components to a carrier comprises temporarily attaching the electronic components to the carrier with the adhesive.
8. The method of claim 6 wherein each respective active surface comprises bond pads, and said attaching electronic components to a carrier comprises attaching the respective active surface of each of the electronic components to the adhesive.
9. The method of claim 6 wherein said laminating a dielectric sheet around the electronic components comprises flowing the dielectric sheet around the electronic components and to the adhesive.
10. The method of claim 6 , comprising after said laminating, cutting the dielectric sheet to conform to a shape of the carrier.
11. The method of claim 6 , comprising, after said laminating a dielectric sheet:
removing the carrier and the adhesive; and
applying a buildup dielectric layer to the respective active surface of each of the electronic components and to the second surface of the package body; and
forming a circuit pattern on the buildup dielectric layer.
12. The method of claim 11 , comprising:
forming a second buildup dielectric layer on the buildup dielectric layer and the circuit pattern;
forming a second circuit pattern on the second buildup dielectric layer that is electrically connected to the circuit pattern; and
attaching a package interconnection structure to the second circuit pattern at a location directly beneath one of the integrated circuit chips.
13. The method of claim 11 , comprising, after said applying a buildup dielectric layer, forming a via aperture through the applied buildup dielectric layer.
14. A method of forming an electronic component package, the method comprising:
attaching electronic components having height dimensions of at least H to a carrier, where the attached electronic components are integrated circuit (IC) chips that each have a width dimension in a first direction greater than a respective height dimension and that are spaced no more than distance W apart in the first direction, where W is no more than 100 micrometers (μm), and wherein the ratio of H to W is at least four;
laminating a dielectric sheet around the electronic components, said laminating comprising:
filling the spaces between the attached electronic components with the dielectric sheet; and
pressing the dielectric sheet onto the electronic components and simultaneously heating the dielectric sheet to cause the dielectric sheet to flow around the electronic components,
wherein the dielectric sheet forms a package body enclosing the electronic components, where the package body comprises a first thickness for those portions of the package body in the spaces between the electronic components and a second thickness, less than the first thickness, for those portions of the package body over the attached electronic components;
removing the carrier;
attaching a buildup dielectric layer to a respective active surface of each of the electronic components and to the package body;
forming a circuit pattern on the buildup dielectric layer; and
cutting the package body and the buildup dielectric layer to singulate the electronic component package.
15. The method of claim 14 wherein H is no greater than 500 μm.
16. The method of claim 14 wherein H is no less than 400 μm.
17. The method of claim 14 , comprising attaching an adhesive to the carrier, and wherein said attaching electronic components to a carrier comprises temporarily attaching the electronic components to the adhesive.
18. The method of claim 14 , comprising:
forming a second buildup dielectric layer on the buildup dielectric layer and the circuit pattern;
forming a second circuit pattern on the second buildup dielectric layer that is electrically connected to the circuit pattern; and
attaching a package interconnection structure to the second circuit pattern at a location directly beneath one of the integrated circuit chips.
19. The method of claim 14 , comprising after said laminating, cutting the dielectric sheet to conform to a shape of the carrier.
20. The method of claim 14 , comprising after said attaching a buildup dielectric layer, forming a via aperture through the attached buildup dielectric layer.