Method of forming a plurality of electronic component packages
A method of forming a plurality of electronic component packages includes attaching electronic components to a carrier, wherein high aspect ratio spaces exist between the electronic components. A dielectric sheet is laminated around the electronic components thus filling the spaces and forming a package body. The spaces are completely and reliably filled by the dielectric sheet and thus the package body has an absence of voids. Further, an upper surface of the package body is planar, i.e., has an absence of ripples or other non-uniformities. Further, lamination of the dielectric sheet is performed with a low cost lamination system.
1. A method of forming an electronic component package, the method comprising:
attaching a plurality of integrated circuit (IC) chips to a carrier at a spacing no more than 100 micrometers (μm) apart in a first direction, wherein each of the IC chips has a height dimension of at least 400 μm and a width dimension in the first direction greater than the height dimension;
laminating a dielectric sheet around the IC chips, said laminating comprising pressing the dielectric sheet onto the attached IC chips to cause the dielectric sheet to flow around the attached IC chips and to fill the spaces between the attached IC chips, wherein the dielectric sheet forms a package body surrounding the IC chips;
removing the carrier;
forming a buildup dielectric layer on a respective active surface of each of the IC chips and on the package body;
forming a circuit pattern on the buildup dielectric layer; and
cutting at least the package body and the buildup dielectric layer to singulate the electronic component package.
2. The method of claim 1 , wherein the package body covers at least five sides of each of the IC chips.
3. The method of claim 2 , wherein the at least five sides of each of the IC chips comprise four lateral sides and an active side of each of the IC chips.
4. The method of claim 2 , wherein the package body comprises a first thickness for those portions of the package body in the spaces between the attached IC chips, and a second thickness, less than the first thickness, for those portions of the package body over the attached IC chips.
5. The method of claim 1 , comprising:
forming a second buildup dielectric layer on the buildup dielectric layer and the circuit pattern;
forming a second circuit pattern on the second buildup dielectric layer and electrically connected to the circuit pattern; and
attaching a package interconnection structure to the second circuit pattern at a location directly vertically aligned with one of the IC chips.
6. The method of claim 1 , comprising after said laminating the dielectric sheet, cutting the dielectric sheet to conform to the shape of the carrier.
7. The method of claim 1 , comprising after said forming the buildup dielectric layer, forming a via aperture through the formed buildup dielectric layer.
8. A method of forming an electronic component package, the method comprising:
attaching a plurality of integrated circuit (IC) chips to a carrier at a spacing no more than 100 micrometers (μm) apart in a first direction, wherein each of the IC chips has a height dimension of at least 400 μm and a width dimension in the first direction greater than the height dimension;
laminating a dielectric sheet around the IC chips, said laminating comprising pressing the dielectric sheet onto the attached IC chips to cause the dielectric sheet to flow around the attached IC chips and to fill the spaces between the attached IC chips, wherein the dielectric sheet forms a package body that encloses at least five sides of each of the IC chips and comprises:
a first planar surface; and
a second planar surface that is coplanar with a respective surface of each of the IC chips,
wherein the package body comprises a first thickness for those portions of the package body in spaces between the IC chips and a second thickness, less than the first thickness, for those portions of the package body over the IC chips.
9. The method of claim 8 , wherein the at least five sides of each of the IC chips comprise four lateral sides and an active side of each of the IC chips.
10. The method of claim 8 , wherein:
said attaching the plurality of IC chips to the carrier comprises attaching the plurality of IC chips to the carrier with an adhesive; and
said laminating a dielectric sheet around the IC chips comprises flowing the dielectric sheet around the IC chips and to the adhesive.
11. The method of claim 8 , comprising after said laminating the dielectric sheet around the IC chips, cutting the dielectric sheet to conform to the shape of the carrier.
12. The method of claim 8 , comprising after said laminating the dielectric sheet around the IC chips:
removing the carrier;
applying a buildup dielectric layer to the second planar surface of the package body and to an active surface of each of the IC chips; and
forming a circuit pattern on the buildup dielectric layer.
13. The method of claim 12 , comprising:
forming a second buildup dielectric layer on the buildup dielectric layer and the circuit pattern;
forming a second circuit pattern on the second buildup dielectric layer that is electrically connected to the circuit pattern; and
attaching a package interconnection structure to the second circuit pattern at a location directly vertically aligned with one of the IC chips.
14. The method of claim 13 , comprising after said forming the buildup dielectric layer, forming a via aperture through the formed buildup dielectric layer.
15. A method of forming an electronic component package, the method comprising:
attaching a plurality of integrated circuit (IC) chips to a carrier at a spacing no more than W apart in a first direction, wherein each of the IC chips has a height dimension of at least H and a width dimension in the first direction greater than H, wherein W is no more than 100 micrometers (μm) and the ratio of H to W is at least four;
laminating a dielectric sheet around the IC chips, said laminating comprising pressing the dielectric sheet onto the attached IC chips to cause the dielectric sheet to flow around the attached IC chips and to fill the spaces between the attached IC chips, wherein:
the dielectric sheet forms a package body surrounding the IC chips; and
the package body comprises a thickness of at least H for those portions of the package body in the spaces between the IC chips;
removing the carrier;
forming a buildup dielectric layer on a respective active surface of each of the IC chips and on the package body;
forming a circuit pattern on the buildup dielectric layer; and
cutting at least the package body and the buildup dielectric layer to singulate the electronic component package.
16. The method of claim 15 , wherein H is no greater than 500 μm.
17. The method of claim 15 , comprising attaching an adhesive to the carrier, and wherein said attaching the plurality of IC chips to the carrier comprises temporarily attaching the IC chips to the adhesive.
18. The method of claim 15 , comprising:
forming a second buildup dielectric layer on the buildup dielectric layer and the circuit pattern;
forming a second circuit pattern on the second buildup dielectric layer that is electrically connected to the circuit pattern; and
attaching a package interconnection structure to the second circuit pattern at a location directly vertically aligned with one of the IC chips.
19. The method of claim 15 , comprising after said laminating the dielectric sheet around the IC chips, cutting the dielectric sheet to conform to the shape of the carrier.
20. The method of claim 15 , comprising after said forming a buildup dielectric layer, forming a via aperture through the formed buildup dielectric layer.