Semiconductor device and method of manufacturing thereof

1. A semiconductor device comprising:

a substrate having a top substrate surface, a bottom substrate surface, and lateral substrate surfaces extending between the top and bottom substrate surfaces;

a metal plane on the top substrate surface, the metal plane comprising first and second apertures extending completely and vertically through the metal plane;

a semiconductor die on the top substrate surface and positioned within the first aperture of the metal plane, the semiconductor die having a top die surface, a bottom die surface, and lateral die side surfaces extending between the top and bottom die surfaces, wherein the bottom die surface is coupled to the top substrate surface; and

an encapsulating material that encapsulates at least a portion of the lateral die side surfaces and at least a portion of the top substrate surface, wherein the encapsulating material extends through the second aperture of the metal plane,

wherein:

the second aperture is entirely laterally bounded by the metal plane; and

the second aperture is free of electronic components.

2. The semiconductor device of claim 1 , wherein the encapsulating material extends through the second aperture of the metal plane to the top substrate surface.

3. The semiconductor device of claim 2 , wherein the encapsulating material completely fills the second aperture of the metal plane.

4. The semiconductor device of claim 1 , wherein the encapsulating material extends into the first aperture of the metal plane.

5. The semiconductor device of claim 1 , wherein no portion of the metal plane is directly below the semiconductor die.

6. The semiconductor device of claim 1 , wherein no portion of the metal plane is lower than the semiconductor die.

7. The semiconductor device of claim 1 , wherein the metal plane comprises a top metal plane surface that is at least as high as the top die surface.

8. The semiconductor device of claim 1 , comprising a conductive column that extends upward from the metal plane and comprises a top column surface that is at least as high as the top die surface, wherein the encapsulating material directly contacts and entirely laterally surrounds the conductive column.

9. The semiconductor device of claim 1 , wherein a lateral surface of the metal plane is exposed from the encapsulating material, and further comprising a conductive shield coupled to the lateral surface of the metal plane.

10. The semiconductor device of claim 1 , wherein the encapsulating material completely laterally surrounds the metal plane.

11. The semiconductor device of claim 1 , wherein the metal plane comprises a plurality of additional apertures that extend completely through the metal plane and are entirely filled with the encapsulating material, wherein each of the plurality of additional apertures is entirely laterally bounded by the metal plane.

12. A semiconductor device comprising:

a substrate having a top substrate surface, a bottom substrate surface, and lateral substrate surfaces extending between the top and bottom substrate surfaces;

a metal layer on the top substrate surface, the metal layer comprising a first section comprising first and second apertures extending completely through the first section, and a second section electrically isolated from the first section and comprising a third aperture extending completely through the second section;

a semiconductor die on the top substrate surface and positioned within the first aperture of the first section, the semiconductor die having a top die surface, a bottom die surface, and lateral die side surfaces extending between the top and bottom die surfaces, wherein the bottom die surface is coupled to the top substrate surface; and

an encapsulating material that encapsulates at least a portion of the lateral die side surfaces and at least a portion of the top substrate surface, wherein the encapsulating material fills the second aperture of the first section and the third aperture of the second section.

13. The semiconductor device of claim 12 , wherein the metal layer covers at least half of the substrate.

14. The semiconductor device of claim 12 , wherein the first section and second section of the metal layer laterally surround the semiconductor die.

15. The semiconductor device of claim 12 , wherein the first section is configured to be electrically coupled to a first power supply signal, and the second section is configured to be electrically coupled to a second power supply signal different from the first power supply signal.

16. The semiconductor device of claim 15 , wherein the first power supply signal comprises a ground signal, and the second power supply signal comprises a non-ground signal power supply signal.

17. A semiconductor device comprising:

a substrate having a top substrate surface, a bottom substrate surface, and lateral substrate surfaces extending between the top and bottom substrate surfaces;

a metal layer on the top substrate surface, the metal layer comprising first and second apertures extending completely and vertically through the metal layer;

a semiconductor die on the top substrate surface and positioned within the first aperture of the metal layer, the semiconductor die having a top die surface, a bottom die surface, and lateral die side surfaces extending between the top and bottom die surfaces, wherein the bottom die surface is coupled to the top substrate surface; and

an encapsulating material that encapsulates at least a portion of the lateral die side surfaces and at least a portion of the top substrate surface, wherein the encapsulating material extends into the second aperture of the metal layer,

wherein:

a metal surface exposed at a top surface of the encapsulating material is electrically connected to the metal layer;

the second aperture is entirely laterally bounded by the metal layer; and

the second aperture is free of electronic components.

18. The semiconductor device of claim 17 , wherein the exposed metal surface is a top surface of the metal layer.

19. The semiconductor device of claim 17 , wherein the exposed metal surface is a top surface of a conductive column that is attached to the metal layer, and the encapsulating material directly contacts and entirely laterally surrounds the conductive column.

20. The semiconductor device of claim 17 , comprising a second metal surface exposed at the top surface of the encapsulating material and electrically connected to the metal layer, and wherein:

the metal surface is electrically connected to a first section of the metal layer and a first power supply signal; and

the second metal surface is electrically connected to a second section of the metal layer and a second power supply signal.