Semicondutor device with through-silicon via-less deep wells
View Patent ↗Methods and systems for a semiconductor device with through-silicon via-less deep wells are disclosed and may include forming a mask pattern on a silicon carrier, etching wells in the silicon carrier, and forming metal contacts in the etched wells, wherein the metal contacts comprise a plurality of deposited metal layers. Redistribution layers may be formed on a subset of the contacts and a dielectric layer may be formed on the silicon carrier and formed redistribution layers. Vias may be formed through the dielectric layer to a second subset of the contacts and second redistribution layers may be formed on the dielectric layer. A semiconductor die may be electrically coupled to the second formed redistribution layers and formed vias. The semiconductor die and top surface of the dielectric layer may be encapsulated and the silicon carrier may be thinned to a thickness of the contacts or may be completely removed.
1. A method for semiconductor packaging, the method comprising:
providing a silicon carrier comprising:
wells at a first surface of the silicon carrier; and
conductive interconnection structures within the wells;
forming a signal distribution structure on the silicon carrier, the signal distribution structure comprising:
a conductive layer comprising traces that are electrically connected to the conductive interconnection structures;
a dielectric layer on the conductive layer; and
vias through the dielectric layer to the traces of the conductive layer;
electrically coupling a semiconductor die to the traces of the conductive layer;
encapsulating at least lateral sides of the semiconductor die and a top surface of the signal distribution structure in an encapsulating material; and
thinning the silicon carrier to expose a first end surface of the conductive interconnection structures and to expose at least a portion of a second surface of the conductive interconnection structures.
2. The method according to claim 1 , wherein said thinning the silicon carrier comprises thinning the silicon carrier until all silicon of the silicon carrier has been removed.
3. The method according to claim 1 , wherein the provided silicon carrier comprises a barrier metal directly on the conductive interconnection structures.
4. The method according to claim 1 , wherein the conductive interconnection structures in the wells comprise solder within the wells.
5. The method according to claim 1 , wherein the exposed at least a portion of the second surfaces of the conductive interconnection structures comprises a sloped sidewall.
6. The method according to claim 1 , wherein the provided silicon carrier comprises a barrier metal on the conductive interconnection structures and on the first surface of the silicon carrier, the method further comprising removing at least a portion of the barrier metal.
7. The method according to claim 1 , wherein the conductive interconnection structures within the wells of the provided silicon carrier directly contact silicon of the provided silicon carrier.
8. The method according to claim 1 , comprising thinning the encapsulating material to expose the semiconductor die.
9. The method according to claim 1 , wherein the provided silicon carrier includes no electronic devices.
10. A method for semiconductor packaging, the method comprising:
providing a silicon carrier having no electronic devices and comprising:
wells at a first surface of the silicon carrier;
conductive interconnection structures within the wells;
a signal distribution structure comprising:
a conductive layer comprising traces that are electrically connected to the conductive interconnection structures;
a dielectric layer on the conductive layer; and
vias through the dielectric layer to the traces of the conductive layer;
electrically coupling a semiconductor die to the traces of the conductive layer;
thinning the silicon carrier to expose at least a first surface of the conductive interconnection structures; and
encapsulating at least lateral sides of the semiconductor die and a top surface of the signal distribution structure in an encapsulating material.
11. The method according to claim 10 , wherein said thinning the silicon carrier comprises thinning the silicon carrier to expose at least a portion of a second surface of the conductive interconnection structures.
12. The method according to claim 11 , wherein said thinning the silicon carrier comprises thinning the silicon carrier until all silicon of the silicon carrier has been removed.
13. The method according to claim 11 , wherein the exposed at least a portion of the second surfaces of the conductive interconnection structures comprises a sloped sidewall.
14. The method according to claim 10 , wherein the provided silicon carrier comprises a barrier metal directly on the conductive interconnection structures.
15. The method according to claim 10 , wherein the provided silicon carrier comprises a barrier metal on the conductive interconnection structures and on a first surface of the silicon carrier, the method further comprising removing at least a portion of the barrier metal.
16. The method according to claim 10 , wherein the conductive interconnection structures within the wells of the provided silicon carrier directly contact silicon of the provided silicon carrier.
17. The method according to claim 10 , comprising thinning the encapsulating material to expose the semiconductor die.
18. The method according to claim 10 , wherein the conductive interconnection structures comprise metal pads.