Semiconductor package thermal tape window frame for heat sink attachment
View Patent ↗The present invention is directed to a semiconductor packaging solution wherein a high K thermal material such as a grease or gel is placed in a controlled thin bond line between the semiconductor die of the package and a heat sink in a direct manner using a thermal tape window frame as a low cost mechanical attachment mechanism. As the main thermal dissipation path is between the backside of the semiconductor die and the heat sink, a high K TIM material can be used to maximize thermal dissipation in a manner that does not require expensive mechanical attachment methods.
1. A semiconductor package, comprising:
a base package which includes a package body defining a body seating plane, and at least one semiconductor die which is partially encapsulated by the package body, the semiconductor die having a portion which protrudes from the package body and defines a die seating plane which is spaced from the body seating plane by a first prescribed distance; and
a frame defining opposed top and bottom surfaces and a window which extends between the top and bottom surfaces, the frame being attached to the base package such that the window and the package body collectively define a cavity in which the portion of the semiconductor die protruding from the package body resides;
the frame having a thickness between the top and bottom surfaces thereof which is selected such that the top surface of the frame is spaced from the die seating plane by a second prescribed distance.
2. The semiconductor package of claim 1 wherein the frame is formed from a layer of thermal tape.
3. The semiconductor package of claim 1 wherein the cavity is filled with a high K thermal interface material which completely covers the portion of the semiconductor die protruding from the package body and defining the die seating plane.
4. The semiconductor package of claim 3 further in combination with a heat sink which is attached to the frame in a manner wherein the thermal interface material defines a bond line between the heat sink and the die seating plane of the semiconductor die which is of a bond line thickness substantially equal to the second prescribed distance.
5. The semiconductor package of claim 4 wherein:
the bottom surface of the frame includes an adhesive layer applied thereto which is secured to the body seating plane defined by the package body; and
the top surface of the frame includes an adhesive layer applied thereto which is secured to the heat sink.
6. The semiconductor package of claim 5 wherein the frame is formed from a layer of thermal tape.
7. The semiconductor package of claim 1 wherein the base package is an FCmBGA package.
8. The semiconductor package of claim 1 wherein the first prescribed distance and the second prescribed distance are substantially equal to each other.
9. A semiconductor package, comprising:
a base package comprising a substrate defining a top surface and at least one semiconductor die electrically connected to the substrate and defining a die seating plane which is spaced from the top surface of the substrate by a first prescribed distance; and
a frame defining opposed top and bottom surfaces and a window which extends between the top and bottom surfaces, the frame being attached to the base package such that the window and the substrate collectively define a cavity in which the semiconductor die resides, the cavity being filled with a high K thermal interface material which completely covers the semiconductor die;
the frame having a thickness between the top and bottom surfaces thereof which is selected such that the top surface of the frame is spaced from the die seating plane by a second prescribed distance.
10. The semiconductor package of claim 9 wherein the frame is formed from a layer of thermal tape.
11. The semiconductor package of claim 9 further in combination with a heat sink which is attached to the frame in a manner wherein the thermal interface material defines a bond line between the heat sink and the die seating plane of the semiconductor die which is of a bond line thickness substantially equal to the second prescribed distance.
12. The semiconductor package of claim 11 wherein:
the bottom surface of the frame includes an adhesive layer applied thereto which is secured to the top surface defined by the substrate; and
the top surface of the frame includes an adhesive layer applied thereto which is secured to the heat sink.
13. The semiconductor package of claim 12 wherein the frame is formed from a layer of thermal tape.
14. The semiconductor package of claim 9 wherein the base package is a Bare Die FCBGA package.
15. The semiconductor package of claim 9 wherein the first prescribed distance exceeds the second prescribed distance.
16. A semiconductor package, comprising:
a base package comprising a substrate and at least one semiconductor die electrically connected to the substrate and defining a die seating plane;
a frame defining opposed top and bottom surfaces and a window which extends between the top and bottom surfaces, the frame being attached to the base package such that the window and the substrate collectively define a cavity in which the semiconductor die resides, the frame having a thickness between the top and bottom surfaces thereof which is selected such that the top surface of the frame is spaced from the die seating plane by a prescribed distance, with the cavity being filled with a thermal interface material which covers the semiconductor die; and
a heat sink which is attached to the frame in a manner wherein the thermal interface material defines a bond line between the heat sink and the die seating plane of the semiconductor die which is of a bond line thickness substantially equal to the prescribed distance.
17. The semiconductor package of claim 16 wherein:
the bottom surface of the frame includes an adhesive layer applied thereto which is secured to the substrate; and
the top surface of the frame includes an adhesive layer applied thereto which is secured to the heat sink.
18. The semiconductor package of claim 17 wherein the frame is formed from a layer of thermal tape.
19. The semiconductor package of claim 16 wherein the base package is selected from one of an FCmBGA package and a Bare Die FCBGA package.