Wafer level fan out package
View Patent ↗A wafer level fan out package includes a semiconductor die having a first surface, a second surface, and a third surface. A stiffener is disposed on the third surface of the semiconductor die. A conductive via passes through the stiffener. First and second electrically conductive patterns electrically connected to the conductive via are disposed on the first and second surfaces of the semiconductor die and stiffener. Solder balls are electrically connected to the first or second electrically conductive patterns.
1. A wafer level fan out package comprising:
a semiconductor die comprising:
a first surface;
a second surface opposed to the first surface, the second surface comprising a bond pad; and
a third surface coupling the first and second surfaces to each other;
a stiffener extending outward from the third surface of the semiconductor die;
a conductive via passing through the stiffener, wherein the conductive via comprises a through hole;
a first electrically conductive pattern coupled to the first surface of the semiconductor die and to the conductive via;
a second electrically conductive pattern coupled to the second surface of the semiconductor die, the second electrically conductive pattern coupling the bond pad to the conductive via;
a first passivation layer coupled to the first electrically conductive pattern and filling the through hole of the conductive via; and
a second passivation layer coupled to the second electrically conductive pattern and to the first passivation layer, the second passivation layer being a different passivation layer than the first passivation layer.
2. The wafer level fan out package as claimed in claim 1 , wherein the stiffener comprises:
a first surface flush with the first surface of the semiconductor die; and
a second surface flush with the second surface of the semiconductor die.
3. The wafer level fan out package as claimed in claim 2 , wherein the first electrically conductive pattern is coupled to the first surface of the stiffener.
4. The wafer level fan out package as claimed in claim 2 , wherein the second electrically conductive pattern is coupled to the second surface of the stiffener.
5. The wafer level fan out package as claimed in claim 1 , wherein a solder ball is coupled to the first electrically conductive pattern.
6. The wafer level fan out package as claimed in claim 1 , wherein a solder ball is coupled to the second electrically conductive pattern.
7. The wafer level fan out package as claimed in claim 1 , wherein the first passivation layer comprises an opening to expose the first electrically conductive pattern.
8. The wafer level fan out package as claimed in claim 1 , further comprising a first electric insulation layer between the first electrically conductive pattern and the first surface of the semiconductor die.
9. The wafer level fan out package as claimed in claim 1 , further comprising a second electric insulation layer between the second electrically conductive pattern and the second surface of the semiconductor die.
10. The wafer level fan out package as claimed in claim 1 , wherein a stack package is electrically coupled to the second electrically conductive pattern.
11. A wafer level fan out package comprising:
a semiconductor die comprising:
a first surface;
a second surface opposed to the first surface, the second surface comprising a bond pad and a Micro Electro Mechanical Systems (MEMS) device; and
a third surface coupling the first and second surfaces to each other;
a stiffener extending outward from the third surface of the semiconductor die;
a conductive via passing through the stiffener;
an electrically conductive pattern coupling the bond pad to the conductive via;
a first passivation layer coupled to the first surface of the semiconductor die; and
a second passivation layer coupled to the second surface of the semiconductor die, the second passivation layer comprising a MEMS opening exposing the MEMS device.
12. The wafer level fan out package as claimed in claim 11 , wherein the MEMS opening is covered with a third passivation layer.
13. The wafer level fan out package as claimed in claim 12 , wherein the third passivation layer is transparent.
14. A wafer level fan out package comprising:
a semiconductor die comprising:
a first surface;
a second surface opposed to the first surface, the second surface comprising a bond pad and a Micro Electro Mechanical Systems (MEMS) device; and
a third surface coupling the first and second surfaces to each other;
a stiffener extending outward from the third surface of the semiconductor die and exposing the first and second surfaces of the semiconductor die;
a conductive via passing through the stiffener;
a first electrically conductive pattern coupled to the first surface of the semiconductor die and to the conductive via; and
a second electrically conductive pattern coupled to the second surface of the semiconductor die, the second electrically conductive pattern coupling the bond pad to the conductive via.
15. The wafer level fan out package as claimed in claim 14 , wherein the stiffener comprises:
a first surface flush with the first surface of the semiconductor die; and
a second surface flush with the second surface of the semiconductor die.
16. The wafer level fan out package as claimed in claim 15 , wherein the first electrically conductive pattern is coupled to the first surface of the stiffener and the second electrically conductive pattern is coupled to the second surface of the stiffener.