Semiconductor package structure for improving die warpage and manufacturing method thereof
View Patent ↗A semiconductor die package includes a semiconductor die, a film for improving die warpage bonded to a first face of the semiconductor die, a plurality of electrically conductive bumps formed on a second face of the semiconductor die, a substrate onto which the electrically conductive bumps of the second face of the semiconductor die are bonded to electrically connect the semiconductor die and the substrate, and a mold compound applied these components to form an exposed surface of the semiconductor die package that is coplanar with an exposed surface of the film.
1. A semiconductor die package comprising:
a semiconductor die having a first face, a second face opposite the first face, and a die edge face joining the first face to the second face;
a film that reduces warpage of the semiconductor die, the film having a first surface, a second surface opposite the first surface, and a film edge surface joining the first surface to the second surface, the first surface of the film bonded to and covering the first face of the semiconductor die, and wherein the film is a single-layer, self-adhesive film;
a plurality of electrically conductive bumps formed on the second face of the semiconductor die;
a substrate having a top surface onto which the semiconductor die is bonded using the plurality of electrically conductive bumps that electrically interconnect the semiconductor die and the substrate;
one or more interconnects on the top surface of the substrate; and
a mold compound covering the substrate and directly contacting the film edge surface and the die edge face, wherein a top surface of the mold compound is coplanar with the second surface of the film, and wherein the mold compound encompasses the one or more interconnects such that a top surface of the one or more interconnects does not extend beyond the top surface of the mold compound.
2. The semiconductor die package according to claim 1 , wherein the film has a thickness in a range of 10 μm to 100 μm.
3. A semiconductor die package comprising:
a substrate having a first surface;
a semiconductor die having a first face, a second face opposite the first face, and a die edge face joining the first face to the second face;
a plurality of conductive elements bonding and electrically interconnecting the second face of the semiconductor die to the first surface of the substrate;
a film that reduces warpage of the semiconductor die, the film having a first surface, a second surface opposite the first surface, and a film edge surface joining the first surface to the second surface, the first surface of the film bonded to and covering the first face of the semiconductor die, and wherein the film is a single-layer, self-adhesive film;
one or more interconnects on the first surface of the substrate; and
a mold compound directly contacting the film edge surface and the die edge face, and filling a region between the first surface of the substrate and the second surface of the semiconductor die, wherein a top surface of the mold compound is coplanar with the second surface of the film, and wherein the mold compound encompasses the one or more interconnects such that a top surface of the one or more interconnects does not extend beyond the top surface of the mold compound.
4. The semiconductor die package according to claim 3 , wherein the film has a thickness in a range of 10 μm to 100 μm.
5. The semiconductor die package according to claim 3 , wherein the second face of the semiconductor die comprises one or more circuit elements electrically connected to the plurality of conductive elements.
6. A semiconductor die package comprising:
a semiconductor die having a first face, a second face opposite the first face, and a die edge face joining the first face to the second face;
a film that reduces warpage of the semiconductor die, the film having a first surface covering the first face of the semiconductor die, a second surface opposite the first surface, and a film edge surface joining the first surface to the second surface, wherein the film is a single-layer, self-adhesive film;
a plurality of conductive elements attached to and extending outward from the second face of the semiconductor die;
a substrate having a top surface onto which the semiconductor die is bonded using the plurality of conductive elements that electrically interconnect circuitry of the semiconductor die and the substrate;
one or more interconnects on the top surface of the substrate; and
a mold compound directly contacting and covering the film edge surface and the plurality of conductive elements, and exposing the second surface of the film opposite the first surface of the film, wherein a top surface of the mold compound is coplanar with the second surface of the film, and wherein the mold compound encompasses the one or more interconnects such that a top surface of the one or more interconnects does not extend beyond the top surface of the mold compound.
7. The semiconductor die package according to claim 6 , wherein the second face of the semiconductor die comprises one or more circuit elements electrically connected to the plurality of conductive elements.
8. The semiconductor die package according to claim 6 , wherein the film has a thickness in a range of 10 μm to 100 μm.
9. The semiconductor die package according to claim 1 , wherein the mold compound directly covers the film edge surface and the die edge face, and wherein the second surface of the film is exposed by the mold compound.
10. The semiconductor die package according to claim 3 , wherein the mold compound directly covers the film edge surface, the die edge face, and the substrate, and wherein the second surface of the film is exposed by the mold compound.
11. The semiconductor package according to claim 1 , wherein:
the second surface of the film consists of a single planar surface; and
the top surface of the mold compound is coplanar with the single planar surface of the second surface.
12. The semiconductor package according to claim 1 , wherein:
the second surface of the film and the top surface of the mold compound define an upper, external surface of the semiconductor package; and a lower surface of the substrate defines a lower, external surface of the semiconductor package that is opposite the upper, external surface.
13. The semiconductor package according to claim 3 , wherein:
the second surface of the film consists of a single planar surface; and the top surface of the mold compound is coplanar with the single planar surface of the second surface.
14. The semiconductor package according to claim 3 , wherein:
the second surface of the film and the top surface of the mold compound define an upper, external surface of the semiconductor package; and a second surface of the substrate, opposite the first surface of the substrate, defines a lower, external surface of the semiconductor package.
15. The semiconductor package according to claim 6 , wherein:
the second surface of the film consists of a single planar surface; and the top surface of the mold compound is coplanar with the single planar surface of the second surface.
16. The semiconductor package according to claim 6 , wherein:
the second surface of the film and the top surface of the mold compound define an upper, external surface of the semiconductor package; and a lower surface of the substrate defines a lower, external surface of the semiconductor package that is opposite the upper, external surface.