Semiconductor package and fabricating method thereof
View Patent ↗A semiconductor device structure and a method for making a semiconductor device. As non-limiting examples, various aspects of this disclosure provide various semiconductor package structures, and methods for making thereof, that comprise a thin fine-pitch redistribution structure.
1. A semiconductor device comprising:
a redistribution structure comprising:
an upper redistribution layer comprising:
a first dielectric layer comprising a first dielectric material; and
a first conductive trace; and
a lower redistribution layer comprising:
a second dielectric layer comprising a second dielectric material; and
a second conductive trace electrically coupled to the first conductive trace;
a first semiconductor die attached to an upper side of the redistribution structure;
a second semiconductor die attached to the upper side of the redistribution structure;
a first mold material covering at least the upper side of the redistribution structure and a respective lateral side of each of the first and second semiconductor die;
a substrate comprising an upper substrate side attached to a lower side of the redistribution structure; and
a second mold material covering at least the upper substrate side, a lateral side of the first mold material, and a lateral side of the redistribution structure.
2. The semiconductor device of claim 1 , wherein the first mold material and the second mold material are different materials.
3. The semiconductor device of claim 1 , wherein an outer surface of the first mold material comprises an adhesion enhancement feature that enhances adhesion between the first mold material and the second mold material.
4. The semiconductor device of claim 1 , wherein:
the first mold material comprises a first mold top surface; and
the second mold material comprises a second mold top surface that is coplanar with the first mold top surface.
5. The semiconductor device of claim 1 , comprising:
a first underfill material between the redistribution structure and the first semiconductor die and between the redistribution structure and the second semiconductor die; and
a second underfill material between the substrate and the redistribution structure, wherein the first and second underfill materials are different materials.
6. The semiconductor device of claim 1 , comprising:
a first underfill material between the redistribution structure and the first semiconductor die and between the redistribution structure and the second semiconductor die; and
a second underfill material between the substrate and the redistribution structure, wherein the second underfill material directly contacts the first underfill material.
7. The semiconductor device of claim 1 , comprising an underfill material between the redistribution structure and the first semiconductor die and between the redistribution structure and the second semiconductor die, wherein the underfill material comprises a lateral side that is orthogonal to the upper side of the redistribution structure.
8. The semiconductor device of claim 1 , comprising an underfill material between the redistribution structure and the first semiconductor die and between the redistribution structure and the second semiconductor die, wherein the underfill material comprises a lateral side that is coplanar with the lateral side of the first mold material and the lateral side of the redistribution structure.
9. The semiconductor device of claim 1 , wherein the first dielectric material is an inorganic material, and second dielectric material is an organic material.
10. The semiconductor device of claim 9 , wherein the redistribution structure comprises an oxide layer, different from the first dielectric material, between the first dielectric layer and the second dielectric layer.
11. The semiconductor device of claim 1 , comprising a conductive via extending through the second mold material from the substrate to an upper surface of the second mold material.
12. The semiconductor device of claim 11 , wherein the conductive via comprises a plated metal pillar.
13. The semiconductor device of claim 11 , comprising a third redistribution layer that comprises:
a third dielectric layer comprising a lower planar side that is directly on the second mold material, the first semiconductor die, and the second semiconductor die; and
a third conductive trace on the third dielectric layer and electrically connected to the conductive via.
14. A semiconductor device comprising:
a redistribution structure comprising:
an upper redistribution layer comprising:
a first dielectric layer comprising a first dielectric material; and
a first conductive trace;
a lower redistribution layer comprising:
a second dielectric layer comprising a second dielectric material; and
a second conductive trace electrically coupled to the first conductive trace; and
a conductive pillar extending from the lower redistribution layer and attached to the second conductive trace;
a first semiconductor die attached to an upper side of the redistribution structure; and
a second semiconductor die attached to the upper side of the redistribution structure;
a substrate attached to the conductive pillar;
a first underfill material between the redistribution structure and the first semiconductor die and between the redistribution structure and the second semiconductor die; and
a second underfill material between the substrate and the redistribution structure,
wherein the first and second underfill materials are different materials.
15. The semiconductor device of claim 14 , wherein the second dielectric material and the first dielectric material are different materials.
16. The semiconductor device of claim 14 , wherein the first dielectric material is an inorganic material, and second dielectric material is an organic material.
17. The semiconductor device of claim 16 , wherein the redistribution structure comprises an oxide layer, different from the first dielectric material, between the first dielectric layer and the second dielectric layer.
18. The semiconductor device of claim 14 , comprising:
a mold material; and
a conductive via extending through the mold material from the substrate to an upper surface of the mold material.
19. The semiconductor device of claim 18 , wherein the conductive via comprises a plated metal pillar.
20. The semiconductor device of claim 18 , comprising a third redistribution layer that comprises:
a third dielectric layer comprising a lower planar side that is directly on the mold material, the first semiconductor die, and the second semiconductor die; and
a third conductive trace on the third dielectric layer and electrically connected to the conductive via.