Semiconductor device with embedded semiconductor die and substrate-to-substrate interconnects
A semiconductor device having an embedded semiconductor die and substrate-to-substrate interconnects is disclosed and may include a substrate with a top surface and a bottom surface, a semiconductor die bonded to the top surface of the substrate, a first mold material encapsulating the semiconductor die and at least a portion of the top surface of the substrate, and a first conductive bump that is on the top surface of the substrate and is at least partially encapsulated by the first mold material. An extended substrate may be coupled to the substrate utilizing the first conductive bump. A second conductive bump may be formed on the bottom surface of the substrate, and a second mold material may encapsulate at least a portion of the second conductive bump and at least a portion of the bottom surface of the substrate. A third mold material may be formed between the first mold material and the extended substrate.
1. A method of manufacturing an electronic device, the method comprising:
coupling a semiconductor die to a top side of a substrate, wherein a bottom side of the substrate comprises a plurality of positions for coupling a plurality of bottom side conductive interconnection structures;
forming a plurality of conductive interconnection structures on the top side of the substrate and that are laterally displaced from the semiconductor die;
encapsulating at least a portion of the top side of the substrate, at least a portion of the semiconductor die, and at least a portion of each of the conductive interconnection structures, in an encapsulating material;
planarizing at least a top side of the encapsulating material and a respective top end of each of the conductive interconnection structures such that the planarized top side of the encapsulating material and the respective planarized top end of each of the conductive interconnection structures are coplanar; and
forming a top side interposer above the planarized encapsulating material, wherein said forming the top side interposer comprises:
forming a top side dielectric layer and a top side conductor layer comprising a plurality of top side conductors, wherein each of the plurality of top side conductors is coupled to a respective one of the conductive interconnection structures through at least a respective aperture in the top side dielectric layer; and
forming a second top side dielectric layer and a second top side conductor layer comprising a second plurality of top side conductors, wherein each of the second plurality of top side conductors is coupled to a respective one of the plurality of top side conductors.
2. The method of claim 1 , wherein said planarizing comprises planarizing a top side of the semiconductor die such that the top side of the encapsulating material, the respective top end of each of the conductive interconnection structures, and the top side of the semiconductor die are coplanar.
3. The method of claim 1 , wherein there is no gap between the encapsulating material the top side dielectric layer.
4. The method of claim 1 , wherein said forming the top side dielectric layer and the top side conductor layer comprises sequentially forming the top side dielectric layer and the top side conductor layer.
5. The method of claim 4 , wherein there is a gap between the top side dielectric layer and the second top side dielectric layer.
6. The method of claim 3 , comprising after said forming the top side interposer, forming coupling the plurality of bottom side conductive interconnection structures at the plurality of positions on the bottom side of the substrate.
7. The method of claim 1 , wherein each of the plurality of conductive interconnection structures comprises a copper pillar.
8. A method of manufacturing an electronic device, the method comprising:
coupling a semiconductor die to a top side of a substrate;
forming a plurality of conductive interconnection structures on the top side of the substrate and that are laterally displaced from the semiconductor die;
encapsulating at least a portion of the top side of the substrate, at least a portion of the semiconductor die, and at least a portion of each of the conductive interconnection structures, in an encapsulating material;
removing a portion of the encapsulating material to expose a respective top end of each of the plurality of conductive interconnection structures;
after said removing a portion of the encapsulating material, forming a top side interposer above the encapsulating material, said forming the top side interposer comprising forming a top side dielectric layer and forming a top side conductor layer comprising a plurality of top side conductors; and
after said forming the top side interposer, forming bottom side conductive interconnection structures on a bottom side of the substrate.
9. The method of claim 8 , wherein said forming the top side dielectric layer comprises forming the top side dielectric layer directly on the encapsulating material.
10. The method of claim 9 , wherein said forming the top side dielectric layer comprises forming the top side dielectric layer directly on the semiconductor die.
11. The method of claim 8 , wherein each of the plurality of top side conductors is coupled to a respective one of the conductive interconnection structures through at least a respective aperture in the top side dielectric layer.
12. The method of claim 11 , wherein said forming the top side interposer comprises forming a second top side dielectric layer and a second top side conductor layer comprising a second plurality of top side conductors, wherein each of the second plurality of top side conductors is coupled to a respective one of the plurality of top side conductors.
13. The method of claim 8 , wherein the bottom side conductive interconnection structures are for mounting the electronic device to a board.
14. The method of claim 8 , wherein said removing a portion of the encapsulating material comprises planarizing at least a top side of the encapsulating material and a respective top end of each of the conductive interconnection structures such that the planarized top side of the encapsulating material and the respective planarized top end of each of the conductive interconnection structures are coplanar.
15. A method of manufacturing an electronic device, the method comprising:
providing a semiconductor die coupled to a top side of a substrate;
providing a plurality of conductive interconnection structures on the top side of the substrate and laterally displaced from the semiconductor die;
encapsulating the electronic device with an encapsulating material, the encapsulating material covering at least a portion of the top side of the substrate, at least a portion of the semiconductor die, and at least a portion of each of the conductive interconnection structures;
removing a portion of the encapsulating material to expose a respective end of each of the conductive interconnection structures; and
after said removing the portion of the encapsulating material, forming a bottom side dielectric layer and forming a bottom side conductor layer comprising a plurality of bottom side conductors on a bottom side of the substrate.
16. The method of claim 15 , wherein the bottom side dielectric layer comprises molding material.
17. The method of claim 15 , wherein each of the plurality of bottom side conductors comprises a conductive ball.
18. The method of claim 15 , wherein a bottom surface of the bottom side dielectric layer and a respective bottom surface of each of the plurality of bottom side conductors are coplanar.
19. The method of claim 18 , comprising forming a second bottom side conductor layer comprising a second plurality of bottom side conductors below the bottom side conductor layer, wherein each of the second plurality of bottom side conductors is coupled to a respective one of the plurality of bottom side conductors.
20. The method of claim 15 , comprising forming a top side interposer above the encapsulating material by, at least in part, forming a top side dielectric layer directly on a top side of the encapsulating material.