Flip chip self-alignment features for substrate and leadframe applications

1. A method for semiconductor packaging, the method comprising:

placing bumps of a semiconductor die, each bump comprising a copper pillar with a solder cap, on a plurality of bond fingers of a metal leadframe, wherein each of at least four of the plurality of bond fingers of the metal leadframe corresponding with a respective corner of the semiconductor die comprises at least one curved sidewall recessed self-alignment feature and at least one of the plurality of bond fingers has no recessed self-alignment feature; and

performing a reflow process on the semiconductor die and the leadframe thereby melting the solder caps of the bumps on the semiconductor die such that each of the bumps is pulled into a respective one of the curved sidewall recessed self-alignment features and aligning the bumps on the semiconductor die to the plurality of bond fingers, wherein a width of the bumps prior to said reflow process is no greater than a width of the curved sidewall recessed self-alignment features.

2. The method according to claim 1 , wherein an entire perimeter of each of the plurality of bumps is contacting a mold material.

3. The method according to claim 1 , comprising forming the curved sidewall recessed self-alignment features utilizing a stamping process.

4. The method according to claim 1 , comprising roughing a surface of at least one of the curved sidewall recessed self-alignment features.

5. The method according to claim 1 , comprising roughing at least one surface of at least one of the bond fingers of the metal leadframe.

6. The method according to claim 1 , comprising forming a solder paste in the curved sidewall recessed self-alignment features prior to placing the bumps of the semiconductor die on the plurality of bond fingers of the metal leadframe.

7. The method according to claim 1 , wherein the curved sidewall recessed self-alignment features are elliptical-shaped.

8. The method according to claim 1 , wherein a depth of the curved sidewall recessed self-alignment features is less than 50 microns.

9. The method according to claim 1 , wherein a bottom surface of each of the curved sidewall recessed self-alignment features is curved.

10. The method according to claim 1 , comprising covering the semiconductor die and at least one surface of the bond fingers with encapsulant.

11. The method of claim 1 , wherein the bumps are self-aligned by virtue of displacement of the semiconductor die due to the curved sidewall recessed self-alignment features.

12. An electronic device, the device comprising:

a semiconductor die bonded to a plurality of leads of a metal leadframe, wherein:

each of at least four of the plurality of leads of the metal leadframe corresponding with a respective corner of the semiconductor die comprises at least one curved recessed self-alignment feature and at least one of the plurality of leads has no recessed self-alignment feature;

each of at least four bumps, comprising a copper pillar with a solder cap, of the semiconductor die is bonded within a respective one of the curved recessed self-alignment features; and

an entire perimeter of each of the at least four bumps is contacting an encapsulating material.

13. The device according to claim 12 , wherein a width of the at least four bumps is no greater than a width of the at least four of the curved recessed self-alignment features.

14. The device according to claim 12 , wherein the curved recessed self-alignment features are stamped.

15. The device according to claim 12 , wherein a surface of at least one of the curved recessed self-alignment features is roughened.

16. The device according to claim 12 , wherein at least one surface of at least one of the leads of the metal leadframe is roughened.

17. The device according to claim 12 , wherein the curved recessed self-alignment features are elliptical-shaped.

18. The device according to claim 12 , wherein a depth of the curved recessed self-alignment features is less than 50 microns.

19. The device according to claim 12 , wherein a bottom surface of each of the curved recessed self alignment features is curved.

20. An electronic device, the device comprising:

a semiconductor die bonded to a plurality of leads of a leadframe, wherein:

each of at least four of the plurality of leads corresponding to a respective corner of the semiconductor die comprises at least two curved sidewall recessed self-alignment features and at least one of the plurality of leads has no recessed self-alignment feature, and each of the curved sidewall recessed self-alignment features has no flat surfaces within;

each of at least four bumps, comprising a copper pillar with a solder cap, of the semiconductor die is bonded within a respective one of the curved sidewall recessed self-alignment features; and

a width of the at least four bumps is no greater than a width of the at least four of the curved sidewall recessed self-alignment features.

21. The device according to claim 20 , wherein an entire perimeter of each of the at least four bumps is exposed to encapsulating material.

22. The device according to claim 20 , wherein the at least four bumps are self-aligned by virtue of displacement of the semiconductor die due to the at least four of the curved sidewall recessed self-alignment features.