Method and system for backside dielectric patterning for wafer warpage and stress control

1. A method for semiconductor processing, the method comprising:

in a semiconductor wafer comprising one or more through silicon vias (TSVs) and one or more die:

thinning said wafer to expose said TSVs on a first surface of said semiconductor wafer;

passivating said first surface of said semiconductor wafer by depositing one or more dielectric layers on said first surface;

planarizing the passivated first surface; and

selectively removing portions of said one more dielectric layers to reduce a strain on said semiconductor wafer.

2. The method according to claim 1 , comprising placing metal contacts on said exposed TSVs prior to said selectively removing portions of said one or more dielectric layers.

3. The method according to claim 1 , comprising placing metal contacts on said exposed TSVs after said selectively removing portions of said one or more dielectric layers.

4. The method according to claim 1 , comprising selectively removing said portions of said one more dielectric layers in a radial pattern.

5. The method according to claim 1 , wherein said one or more dielectric layers comprise one or more plasma deposited films.

6. The method according to claim 5 , wherein said one or more plasma deposited films comprise one or more of: a nitride layer and a silicon dioxide layer.

7. The method according to claim 1 , wherein said one or more dielectric layers comprise one or more organic films.

8. The method according to claim 1 , comprising thinning said semiconductor wafer to below a top surface of said TSVs.

9. The method according to claim 1 , comprising selectively removing said one or more dielectric layers utilizing one or more of: a dry etch process, wet chemical etching, and laser ablation.

10. The method according to claim 1 , comprising reducing warpage of said semiconductor wafer by said reducing of said strain.

11. The method according to claim 1 , wherein the semiconductor die comprises an interposer die.

12. The method according to claim 1 , wherein the selectively removing portions of said one more dielectric layers comprises forming grooves in the one or more dielectric layers.

13. The method according to claim 1 , comprising selectively removing said portions of said one more dielectric layers in a checkerboard pattern.

14. A method for semiconductor processing, the method comprising:

passivating a first surface of a semiconductor die by, at least in part, forming one or more dielectric layers over the first surface configured to support contacts for bonding the semiconductor die to a packaging substrate; and

forming stress-relieving features in the one or more dielectric layers.

15. The method according to claim 14 , wherein said passivating and said forming are performed when the die is in wafer form.

16. The method according to claim 14 , wherein said forming stress-relieving features comprises forming grooves in the one or more dielectric layers.

17. The method according to claim 14 , wherein said forming stress-relieving features comprises forming a checkerboard pattern in the one or more dielectric layers.

18. The method according to claim 14 , wherein said forming stress-relieving features comprises removing a portion of the one or more dielectric layers over a non-electrically active region of the die while refraining from removing a portion of the one or more dielectric layers over an electrically active region of the die.

19. The method according to claim 14 , wherein said forming stress-relieving features comprises forming a pattern in a portion of the one or more dielectric layers corresponding to a first region of the semiconductor die that is different from of an input/output region of said semiconductor die.

20. The method according to claim 14 , wherein said forming stress-relieving features comprises selectively removing the one or more dielectric layers utilizing one or more of; a dry etch process, wet chemical etching, and laser ablation.

21. The method according to claim 14 , wherein:

the first surface comprises:

contact zones configured for supporting the contacts; and

contactless zones between the contact zones;

the stress relieving features comprise:

stress relieving zones over the first surface where material is removed from a first dielectric layer of the one or more dielectric layers;

and

forming the stress-relieving features comprises: locating the stress-relieving features over the first surface such that a thickness of the first dielectric layer is greater over a majority of the contactless zones than over the stress relieving zones.

22. The method according to claim 14 , wherein the forming stress-relieving features in the one or more dielectric layers comprises removing a portion of the dielectric layers down to the first surface of the semiconductor die.

23. A method for semiconductor processing, the method comprising:

passivating a first surface of a semiconductor die by, at least in part, forming one or more dielectric layers over the first surface; and

forming stress-relieving features in the one or more dielectric layers wherein said forming stress-relieving features comprises forming a pattern in a portion of the one or more dielectric layers corresponding to a first region of the semiconductor die that is different from of an input/output region of said semiconductor die.

24. The method according to claim 23 , wherein said forming stress-relieving features comprises forming grooves in the one or more dielectric layers.

25. The method according to claim 23 , wherein said forming stress-relieving features comprises forming a checkerboard pattern in the one or more dielectric layers.

26. The method according to claim 23 , wherein said forming stress-relieving features comprises selectively removing the one or more dielectric layers utilizing one or more of; a dry etch process, wet chemical etching, and laser ablation.