Semiconductor package and method for manufacturing the same
View Patent ↗One embodiment provides a semiconductor package by forming a redistribution layer extending from a bonding pad of a semiconductor chip using a photoresist pattern plated with the seed layer. Fabrication of the semiconductor package is relatively simple thereby shortening a manufacturing time and reducing the manufacturing cost, and which can increase an adhered area of input/output terminals and can prevent delamination by connecting and welding the input/output terminals to a pair of redistribution layers.
1. A semiconductor package comprising:
a semiconductor chip;
a redistribution layer pattern comprising:
a first ring type photoresist pattern around a bonding pad of the semiconductor chip;
a linear photoresist pattern extending from the first ring type photoresist pattern; and
a second ring type photoresist pattern formed at an end of the linear photoresist pattern;
a seed layer comprising:
a first seed layer coupled to the bonding pad of the semiconductor chip;
a second seed layer coupled to the redistribution layer pattern; and
a third seed layer coupled to a passivation film of the semiconductor chip existing in an interior region of the second ring type photoresist pattern;
a first conductive connection member coupling the first seed layer to the second seed layer; and
a second conductive connection member coupling the second seed layer to the third seed layer.
2. The semiconductor package of claim 1 , wherein a shape of the first and second ring type photoresist patterns is selected from a shape consisting of a circular, elliptic and rectangular ring.
3. The semiconductor package of claim 1 , wherein the first and second conductive connection members comprise solder paste.
4. The semiconductor package of claim 1 , wherein the first and second conductive connection members comprise a solder ball.
5. The semiconductor package of claim 1 , wherein the first and second ring type photoresist patterns and the linear photoresist pattern are formed to have the same height.
6. A method for manufacturing a semiconductor package comprising:
patterning a photoresist to form a redistribution layer pattern comprising:
a first ring type photoresist pattern around a bonding pad of a semiconductor chip;
a second ring type photoresist pattern;
a linear photoresist pattern extending from the first ring type photoresist pattern to the second ring type photoresist pattern;
forming a seed layer comprising:
a first seed layer coupled to the bonding pad of the semiconductor chip;
a second seed layer coupled to the redistribution layer pattern; and
a third seed layer coupled to a passivation film of the semiconductor chip within an interior region of the second ring type photoresist pattern.
7. The method of claim 6 wherein the first seed layer is electrically isolated from the second seed layer.
8. The method of claim 7 wherein the second seed layer is electrically isolated from the third seed layer.
9. The method of claim 6 wherein the first seed layer, the second seed layer, and the third seed layer are physically separated from one another.
10. The method of claim 9 further comprising:
coupling the first seed layer to the second seed layer with a first conductive connection member.
11. The method of claim 10 further comprising:
coupling the second seed layer to the third seed layer with a second connection member.
12. The method of claim 11 wherein the second connection member forms an input/output terminal for the semiconductor package.
13. A method for manufacturing a semiconductor package comprising:
coating a surface of a semiconductor chip with a photoresist;
performing exposure and development operations on the photoresist to form a redistribution layer pattern extending from a bonding pad of the semiconductor chip to a predetermined position of the semiconductor chip;
forming a seed layer coupled to the bonding pad of the semiconductor chip, the predetermined position of the semiconductor chip, and the redistribution layer pattern; and
conductively connecting the seed layer on the bonding pad of the semiconductor chip to the seed layer on the predetermined position of the semiconductor chip by conductive connection members.
14. The method of claim 13 , wherein the redistribution layer pattern comprises a first ring type photoresist pattern protruding around the bonding pad of the semiconductor chip.
15. The method of claim 14 , wherein the redistribution layer pattern further comprises a linear photoresist pattern extending from the first ring type photoresist pattern to the predetermined position of the semiconductor chip.
16. The method of claim 15 , wherein the redistribution layer pattern further comprises a second ring type photoresist pattern formed at an end of the linear photoresist pattern.
17. The method of claim 13 , wherein the seed layer comprises a first seed layer coupled to the bonding pad of the semiconductor chip.
18. The method of claim 17 , wherein the seed layer further comprises a second seed layer coupled to the redistribution layer pattern.
19. The method of claim 18 , wherein the seed layer further comprises a third seed layer coupled to a passivation film of the semiconductor chip existing in an interior region of a ring type photoresist pattern of the redistribution layer pattern.
20. The method of claim 19 , wherein the first seed layer is conductively connecting to the second seed layer by a first conductive connection member of the conductive connection members, and
the second seed layer is conductively connected to the third seed layer by a second conductive connection member of the conductive connection members.