IP Library Granted Patent US 10,505,041
Granted Patent B2
US 10,505,041 · App. 15/469,569 · Granted Dec 10, 2019

Semiconductor device having epitaxial layer with planar surface and protrusions

Inventors: Chun-Wei Yu (Tainan, TW); Hsu Ting (Tainan, TW); Chueh-Yang Liu (Tainan, TW); Yu-Ren Wang (Tainan, TW); Kuang-Hsiu Chen (Tainan, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H01L29/7845H01L21/02065H01L21/28123H01L21/823814H01L21/823828H01L21/823864H01L21/823871H01L23/535H01L27/092H01L29/165H01L29/41766H01L29/45H01L29/66545H01L29/7848H01L29/0847
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Quick Facts
Patent No.
US 10,505,041
App. No.
15/469,569
Granted
Dec 10, 2019
Kind
B2
Abstract

A semiconductor device includes: a substrate; a gate structure on the substrate; and an epitaxial layer in the substrate adjacent to the gate structure, in which the epitaxial layer includes a planar surface and protrusions adjacent to two sides of the planar surface. Preferably, a contact plug is embedded in part of the epitaxial layer, and a silicide is disposed under the contact plug, in which a bottom surface of the silicide includes an arc.

Claims (12)

1. A semiconductor device, comprising:

a substrate;

a gate structure on the substrate;

a spacer adjacent to the gate structure;

a contact plug adjacent to the gate structure; and

an epitaxial layer adjacent to the gate structure and under the contact plug, wherein the epitaxial layer comprises a planar surface and a protrusion, both the planar surface and the protrusion are adjacent to two sides of the contact plug, all of the planar surface is higher than a top surface of the substrate, and a tip of the protrusion is higher than the planar surface and contacting a sidewall of the spacer directly.

2. The semiconductor device of claim 1 , further comprising the contact plug embedded in part of the epitaxial layer, wherein a bottom surface of the contact plug comprises an arc.

3. The semiconductor device of claim 2 , further comprising a silicide under the contact plug.

4. The semiconductor device of claim 3 , wherein a bottom surface of the silicide comprises an arc.

5. The semiconductor device of claim 4 , wherein the epitaxial layer comprises silicon phosphide.

6. The semiconductor device of claim 1 , further comprising a contact etch stop layer (CESL) adjacent to the gate structure, wherein the protrusion contacts the CESL directly.

7. The semiconductor device of claim 1 , wherein a tip of the protrusion is higher than a top surface of the substrate.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 26, 2017
From: YU, CHUN-WEI; TING, HSU; LIU, CHUEH-YANG; WANG, YU-REN; CHEN, KUANG-HSIU
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 041745/0558 →
Priority Claims (1)
CN 2015 1 0995716 · Dec 25, 2015 · national
Continuity (2)
Division 15003782 · Jan 21, 2016
Related Publication 20170200824A1 · Jul 13, 2017