IP Library Granted Patent US 10,297,456
Granted Patent B2
US 10,297,456 · App. 15/473,167 · Granted May 21, 2019

Dielectric structures for nitride semiconductor devices

Inventors: Bernard A. Alamariu (Newton, MA); Omair I. Saadat (Cambridge, MA); Tomas Apostol Palacios (Belmont, MA)
Assignee: Massachusetts Institute of Technology
H01L21/28264H01L21/02164H01L21/02175H01L21/02238H01L21/02241H01L21/02255H01L21/823462H01L21/823857H01L29/2003H01L29/513H01L29/517H01L29/7786
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Quick Facts
Patent No.
US 10,297,456
App. No.
15/473,167
Granted
May 21, 2019
Kind
B2
Abstract

A dielectric structure for a nitride semiconductor device and a method of forming the same. A semiconductor device includes at least one semiconductor layer. The at least one semiconductor layer includes a gallium nitride semiconductor material. The semiconductor device also includes an oxidized layer disposed over the at least one semiconductor layer. The oxidized layer includes an oxidized form of the gallium nitride semiconductor of the at least one semiconductor layer. A silicon oxide layer is disposed over the oxidized layer. A gate is disposed over the silicon oxide layer.

Claims (14)

1. A method of forming a semiconductor device, the method comprising:

forming a layer of polysilicon over at least one semiconductor layer, the at least one semiconductor layer including a layer of gallium nitride formed over a layer of aluminum gallium nitride or a layer of indium gallium nitride;

thermally oxidizing the layer of polysilicon to form a layer of silicon oxide; and

thermally oxidizing at least a portion of the layer of gallium nitride to form gallium oxide by introducing oxidizing species through the layer of silicon oxide to form a layer of gallium oxide over the layer of aluminum gallium nitride or the layer of indium gallium nitride.

2. The method of claim 1 , wherein thermally oxidizing the at least a portion of the layer of gallium nitride produces a gallium oxide layer positioned between the at least one semiconductor layer and the layer of silicon oxide and forms an interface with the at least one semiconductor layer.

3. The method of claim 2 , wherein thermally oxidizing the at least a portion of the layer of gallium nitride further comprises forming a layer of gallium oxide that includes beta-Ga 2 O 3 .

4. The method of claim 2 , wherein the interface has a density of interface traps of less than 5×10 12 cm 2 .

5. The method of claim 1 , wherein thermally oxidizing the layer of polysilicon is performed at a temperature of less than approximately 700° C.

6. The method of claim 5 , wherein thermally oxidizing the layer of polysilicon is further performed in a wet environment.

7. The method of claim 1 , wherein forming the layer of polysilicon comprises depositing the layer of polysilicon over the layer of gallium nitride.

8. The method of claim 1 , further comprising forming a gate over the layer of silicon oxide.

9. The method of claim 1 , further comprising forming an insulating layer over the layer of silicon oxide.

10. The method of claim 1 , wherein thermally oxidizing the at least a portion of the layer of gallium nitride occurs at a rate that depends on a thickness of the layer of silicon oxide.

11. The method of claim 1 , wherein forming the layer of polysilicon further comprises forming the layer of polysilicon by low pressure chemical vapor deposition (LPCVD).

Assignments (2)
CONFIRMATORY LICENSE Recorded May 13, 2019
From: MIT
To: NAVY, SECRETARY OF THE UNITED STATES OF AMERICA
Reel/Frame 049166/0447 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 12, 2018
From: ALAMARIU, BERNARD A.; SAADAT, OMAIR I.; PALACIOS, TOMAS APOSTOL
To: MASSACHUSETTS INSTITUTE OF TECHNOLOGY
Reel/Frame 044891/0406 →
Continuity (3)
Continuation In Part PCTUS2015052880 · Sep 29, 2015
Provisional Application 62056724 · Sep 29, 2014
Related Publication 20170301546A1 · Oct 19, 2017