Reducing conflicts in direct mapped caches
A processor includes a processing core to execute a transaction with a memory via a cache and a cache controller, associated with the processor, comprising an index mapper circuit to identify a physical memory address associated with the transaction, wherein the physical memory address comprises a plurality of bits, determine, based on the plurality of bits, a first set of bits encoding a tag value, a second set of bits encoding a page index value, and a third set of bits encoding a line index value, determine, based on the tag value, a bit-placement order for combining the second set of bits and the third set of bits, combine, based on the bit-placement order, the second set of bits and the third set of bits to form an index, and generate, based on the index, a mapping from the physical memory address to a cache line index value identifying a cache line in the cache, wherein the processing core is to access, based on the cache line, a memory location referenced by the physical memory address.
1. A processor comprising:
a processing core to execute a transaction with a memory via a cache; and
a cache controller, associated with the processor, comprising an index mapper circuit to:
identify a physical memory address associated with the transaction, wherein the physical memory address comprises a plurality of bits;
determine, based on the plurality of bits, a first set of bits encoding a tag value, a second set of bits encoding a page index value, and a third set of bits encoding a line index value;
determine, based on the tag value, a bit-placement order for combining the second set of bits and the third set of bits;
combine, based on the bit-placement order, the second set of bits and the third set of bits to form an index, wherein to combine the second set of bits and the third set of bits, the index mapper circuit is to swap at least one bit of the second set of bits with at least one bit of the third set of bits; and
generate, based on the index, a mapping from the physical memory address to a cache line index value identifying a cache line in the cache,
wherein the processing core is to access, based on the cache line, a memory location referenced by the physical memory address.
2. The processor of claim 1 , wherein the cache is a direct mapped cache, and wherein each cache line in the direct mapped cache is identified by a respective cache line index value.
3. The processor of claim 1 , wherein the cache is at least one of a memory-side cache or a last-level cache (LLC).
4. The processor of claim 1 , wherein the tag value is associated with a group of memory addresses to be mapped to the cache.
5. The processor of claim 1 , wherein the index mapper circuit further comprises at least one multiplexer circuit comprising:
a first input node to receive the at least one bit of the second set of bits;
a second input node to receive the at least one bit of the third set of bits; and
a control node to receive the tag value, wherein the at least one multiplexer is to, based on the tag value, swap the at least one bit of the second set of bits with the at least one bit of the third set of bits.
6. The processor of claim 1 , wherein the processor is to at least one of read or write, via the cache line, the memory location referenced by the physical memory address.
7. The processor of claim 1 , wherein the index mapper circuit is to convert, using a first mapping function, a first physical memory address comprising a first tag value, a first page index value, and a first line value to a first cache line index value, and is to convert, using a second mapping function, a second physical memory address comprising a second tag value, the first page index value, and the first line index value to a second cache line index value, and wherein the first cache line index value is different from the second cache line index value.
8. The processor of claim 7 , wherein the first mapping function comprises a first bit-placement order for combining the second set of bits and the third set of bits, and the second mapping function comprises a second bit-placement order for combining the second set of bits and the third set of bits.
9. A system, comprising:
a memory;
a cache; and
a processor, coupled to the memory and the cache, comprising:
a processing core to execute a transaction with the memory via the cache; and
a cache controller, associated with the processor, comprising an index mapper circuit to:
identify a physical memory address associated with the transaction, wherein the physical memory address comprises a plurality of bits;
determine, based on the plurality of bits, a first set of bits encoding a tag value, a second set of bits encoding a page index value, and a third set of bits encoding a line index value;
determine, based on the tag value, a bit-placement order for combining the second set of bits and the third set of bits;
combine, based on the bit-placement order, the second set of bits and the third set of bits to form an index, wherein to combine the second set of bits and the third set of bits, the index mapper circuit is to swap at least one bit of the second set of bits with at least one bit of the third set of bits; and
generate, based on the index, a mapping from the physical memory address to a cache line index value identifying a cache line in the cache,
wherein the processing core is to access, based on the cache line, a memory location referenced by the physical memory address.
10. The system of claim 9 , wherein the cache is a direct mapped cache, and wherein each cache line in the direct mapped cache is identified by a respective cache line index value.
11. The system of claim 9 , wherein the cache is at least one of a memory-side cache or a last-level cache (LLC).
12. The system of claim 9 , wherein the tag value is associated with a group of memory addresses to be mapped to the cache.
13. The system of claim 9 , wherein the index mapper circuit further comprises at least one multiplexer circuit comprising:
a first input node to receive the at least one bit of the second set of bits;
a second input node to receive the at least one bit of the third set of bits; and
a control node to receive the tag value, wherein the at least one multiplexer is to, based on the tag value, swap the at least one bit of the second set of bits with the at least one bit of the third set of bits.
14. The system of claim 9 , wherein the processor is to at least one of read or write, via the cache line, the memory location referenced by the physical memory address.
15. The system of claim 9 , wherein the index mapper circuit is to convert, using a first mapping function, a first physical memory address comprising a first tag value, a first page index value, and a first line value to a first cache line index value, and is to convert, using a second mapping function, a second physical memory address comprising a second tag value, the first page index value, and the first line index value to a second cache line index value, and wherein the first cache line index value is different from the second cache line index value.
16. The system of claim 15 , wherein the first mapping function comprises a first bit-placement order for combining the second set of bits and the third set of bits, and the second mapping function comprises a second bit-placement order for combining the second set of bits and the third set of bits.
17. A method comprising:
identifying, by a processor, a physical memory address of a memory page, wherein the physical memory address comprises a plurality of bits;
determining, based on the plurality of bits, a first set of bits encoding a tag value, a second set of bits encoding a page index value, and a third set of bits encoding a line index value;
determining, based on the tag value, a bit-placement order for combining the second set of bits and the third set of bits;
combining, based on the bit-placement order, the second set of bits and the third set of bits to form an index, wherein the combining comprises swapping at least one bit of the second set of bits with at least one bit of the third set of bits;
generating, based on the index, a mapping from the physical memory address to a cache line index value identifying a cache line in the cache; and
accessing, based on the cache line, a memory location referenced by the physical memory address.
18. The method of claim 17 , wherein the cache is a direct mapped cache, and wherein each cache line in the direct mapped cache is identified by a respective cache line index value.